Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Interconnect framework driver for i.MX SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2019-2020, NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __DT_BINDINGS_INTERCONNECT_IMX8MQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __DT_BINDINGS_INTERCONNECT_IMX8MQ_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define IMX8MQ_ICN_NOC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IMX8MQ_ICS_DRAM		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX8MQ_ICS_OCRAM	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX8MQ_ICM_A53		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX8MQ_ICM_VPU		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX8MQ_ICN_VIDEO	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX8MQ_ICM_GPU		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX8MQ_ICN_GPU		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX8MQ_ICM_DCSS		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX8MQ_ICN_DCSS		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX8MQ_ICM_USB1		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX8MQ_ICM_USB2		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX8MQ_ICN_USB		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX8MQ_ICM_CSI1		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX8MQ_ICM_CSI2		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX8MQ_ICM_LCDIF	16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX8MQ_ICN_DISPLAY	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX8MQ_ICM_SDMA2	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX8MQ_ICN_AUDIO	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX8MQ_ICN_ENET		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX8MQ_ICM_ENET		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX8MQ_ICM_SDMA1	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX8MQ_ICM_NAND		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX8MQ_ICM_USDHC1	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX8MQ_ICM_USDHC2	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX8MQ_ICM_PCIE1	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX8MQ_ICM_PCIE2	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX8MQ_ICN_MAIN		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #endif /* __DT_BINDINGS_INTERCONNECT_IMX8MQ_H */