Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Interconnect framework driver for i.MX SoC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2019, BayLibre
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (c) 2019-2020, NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * Author: Alexandre Bailon <abailon@baylibre.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #ifndef __DT_BINDINGS_INTERCONNECT_IMX8MM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define __DT_BINDINGS_INTERCONNECT_IMX8MM_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define IMX8MM_ICN_NOC		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define IMX8MM_ICS_DRAM		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define IMX8MM_ICS_OCRAM	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX8MM_ICM_A53		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX8MM_ICM_VPU_H1	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX8MM_ICM_VPU_G1	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX8MM_ICM_VPU_G2	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX8MM_ICN_VIDEO	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX8MM_ICM_GPU2D	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX8MM_ICM_GPU3D	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX8MM_ICN_GPU		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX8MM_ICM_CSI		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX8MM_ICM_LCDIF	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX8MM_ICN_MIPI		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX8MM_ICM_USB1		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX8MM_ICM_USB2		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX8MM_ICM_PCIE		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX8MM_ICN_HSIO		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX8MM_ICM_SDMA2	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX8MM_ICM_SDMA3	20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX8MM_ICN_AUDIO	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX8MM_ICN_ENET		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX8MM_ICM_ENET		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX8MM_ICN_MAIN		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX8MM_ICM_NAND		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX8MM_ICM_SDMA1	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX8MM_ICM_USDHC1	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX8MM_ICM_USDHC2	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX8MM_ICM_USDHC3	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #endif /* __DT_BINDINGS_INTERCONNECT_IMX8MM_H */