Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2012-2014,2018,2020 The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define _DT_BINDINGS_QCOM_SPMI_VADC_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) /* Voltage ADC channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define VADC_USBIN				0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define VADC_DCIN				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define VADC_VCHG_SNS				0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define VADC_SPARE1_03				0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define VADC_USB_ID_MV				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define VADC_VCOIN				0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define VADC_VBAT_SNS				0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define VADC_VSYS				0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define VADC_DIE_TEMP				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define VADC_REF_625MV				0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define VADC_REF_1250MV				0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define VADC_CHG_TEMP				0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define VADC_SPARE1				0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define VADC_SPARE2				0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define VADC_GND_REF				0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define VADC_VDD_VADC				0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define VADC_P_MUX1_1_1				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define VADC_P_MUX2_1_1				0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define VADC_P_MUX3_1_1				0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define VADC_P_MUX4_1_1				0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define VADC_P_MUX5_1_1				0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define VADC_P_MUX6_1_1				0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define VADC_P_MUX7_1_1				0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define VADC_P_MUX8_1_1				0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define VADC_P_MUX9_1_1				0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define VADC_P_MUX10_1_1			0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define VADC_P_MUX11_1_1			0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define VADC_P_MUX12_1_1			0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define VADC_P_MUX13_1_1			0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define VADC_P_MUX14_1_1			0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define VADC_P_MUX15_1_1			0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define VADC_P_MUX16_1_1			0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define VADC_P_MUX1_1_3				0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define VADC_P_MUX2_1_3				0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define VADC_P_MUX3_1_3				0x22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define VADC_P_MUX4_1_3				0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define VADC_P_MUX5_1_3				0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define VADC_P_MUX6_1_3				0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define VADC_P_MUX7_1_3				0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define VADC_P_MUX8_1_3				0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define VADC_P_MUX9_1_3				0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define VADC_P_MUX10_1_3			0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define VADC_P_MUX11_1_3			0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define VADC_P_MUX12_1_3			0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define VADC_P_MUX13_1_3			0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define VADC_P_MUX14_1_3			0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define VADC_P_MUX15_1_3			0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define VADC_P_MUX16_1_3			0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define VADC_LR_MUX1_BAT_THERM			0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define VADC_LR_MUX2_BAT_ID			0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define VADC_LR_MUX3_XO_THERM			0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define VADC_LR_MUX4_AMUX_THM1			0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define VADC_LR_MUX5_AMUX_THM2			0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define VADC_LR_MUX6_AMUX_THM3			0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define VADC_LR_MUX7_HW_ID			0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define VADC_LR_MUX8_AMUX_THM4			0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define VADC_LR_MUX9_AMUX_THM5			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define VADC_LR_MUX10_USB_ID			0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define VADC_AMUX_PU1				0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define VADC_AMUX_PU2				0x3b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define VADC_LR_MUX3_BUF_XO_THERM		0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define VADC_LR_MUX1_PU1_BAT_THERM		0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define VADC_LR_MUX2_PU1_BAT_ID			0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define VADC_LR_MUX3_PU1_XO_THERM		0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define VADC_LR_MUX4_PU1_AMUX_THM1		0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define VADC_LR_MUX5_PU1_AMUX_THM2		0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define VADC_LR_MUX6_PU1_AMUX_THM3		0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define VADC_LR_MUX7_PU1_AMUX_HW_ID		0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define VADC_LR_MUX8_PU1_AMUX_THM4		0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define VADC_LR_MUX9_PU1_AMUX_THM5		0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define VADC_LR_MUX10_PU1_AMUX_USB_ID		0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define VADC_LR_MUX3_BUF_PU1_XO_THERM		0x7c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define VADC_LR_MUX1_PU2_BAT_THERM		0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define VADC_LR_MUX2_PU2_BAT_ID			0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define VADC_LR_MUX3_PU2_XO_THERM		0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define VADC_LR_MUX4_PU2_AMUX_THM1		0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define VADC_LR_MUX5_PU2_AMUX_THM2		0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define VADC_LR_MUX6_PU2_AMUX_THM3		0xb5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define VADC_LR_MUX7_PU2_AMUX_HW_ID		0xb6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define VADC_LR_MUX8_PU2_AMUX_THM4		0xb7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define VADC_LR_MUX9_PU2_AMUX_THM5		0xb8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define VADC_LR_MUX10_PU2_AMUX_USB_ID		0xb9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define VADC_LR_MUX3_BUF_PU2_XO_THERM		0xbc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define VADC_LR_MUX1_PU1_PU2_BAT_THERM		0xf0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VADC_LR_MUX2_PU1_PU2_BAT_ID		0xf1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VADC_LR_MUX3_PU1_PU2_XO_THERM		0xf2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VADC_LR_MUX4_PU1_PU2_AMUX_THM1		0xf3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VADC_LR_MUX5_PU1_PU2_AMUX_THM2		0xf4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VADC_LR_MUX6_PU1_PU2_AMUX_THM3		0xf5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VADC_LR_MUX7_PU1_PU2_AMUX_HW_ID		0xf6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define VADC_LR_MUX8_PU1_PU2_AMUX_THM4		0xf7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VADC_LR_MUX9_PU1_PU2_AMUX_THM5		0xf8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VADC_LR_MUX10_PU1_PU2_AMUX_USB_ID	0xf9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VADC_LR_MUX3_BUF_PU1_PU2_XO_THERM	0xfc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* ADC channels for SPMI PMIC5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ADC5_REF_GND				0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ADC5_1P25VREF				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ADC5_VREF_VADC				0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ADC5_VREF_VADC5_DIV_3			0x82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ADC5_VPH_PWR				0x83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ADC5_VBAT_SNS				0x84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ADC5_VCOIN				0x85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ADC5_DIE_TEMP				0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ADC5_USB_IN_I				0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ADC5_USB_IN_V_16			0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ADC5_CHG_TEMP				0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ADC5_BAT_THERM				0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ADC5_BAT_ID				0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ADC5_XO_THERM				0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ADC5_AMUX_THM1				0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ADC5_AMUX_THM2				0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ADC5_AMUX_THM3				0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ADC5_AMUX_THM4				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ADC5_AMUX_THM5				0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ADC5_GPIO1				0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ADC5_GPIO2				0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ADC5_GPIO3				0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ADC5_GPIO4				0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ADC5_GPIO5				0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ADC5_GPIO6				0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ADC5_GPIO7				0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ADC5_SBUx				0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define ADC5_MID_CHG_DIV6			0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ADC5_OFF				0xff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) /* 30k pull-up1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ADC5_BAT_THERM_30K_PU			0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ADC5_BAT_ID_30K_PU			0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ADC5_XO_THERM_30K_PU			0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ADC5_AMUX_THM1_30K_PU			0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ADC5_AMUX_THM2_30K_PU			0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ADC5_AMUX_THM3_30K_PU			0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ADC5_AMUX_THM4_30K_PU			0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ADC5_AMUX_THM5_30K_PU			0x31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ADC5_GPIO1_30K_PU			0x32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ADC5_GPIO2_30K_PU			0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ADC5_GPIO3_30K_PU			0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ADC5_GPIO4_30K_PU			0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ADC5_GPIO5_30K_PU			0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ADC5_GPIO6_30K_PU			0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ADC5_GPIO7_30K_PU			0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ADC5_SBUx_30K_PU			0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* 100k pull-up2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ADC5_BAT_THERM_100K_PU			0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define ADC5_BAT_ID_100K_PU			0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ADC5_XO_THERM_100K_PU			0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ADC5_AMUX_THM1_100K_PU			0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ADC5_AMUX_THM2_100K_PU			0x4e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ADC5_AMUX_THM3_100K_PU			0x4f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ADC5_AMUX_THM4_100K_PU			0x50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ADC5_AMUX_THM5_100K_PU			0x51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ADC5_GPIO1_100K_PU			0x52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ADC5_GPIO2_100K_PU			0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ADC5_GPIO3_100K_PU			0x54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ADC5_GPIO4_100K_PU			0x55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ADC5_GPIO5_100K_PU			0x56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ADC5_GPIO6_100K_PU			0x57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ADC5_GPIO7_100K_PU			0x58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ADC5_SBUx_100K_PU			0x59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* 400k pull-up3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ADC5_BAT_THERM_400K_PU			0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define ADC5_BAT_ID_400K_PU			0x6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define ADC5_XO_THERM_400K_PU			0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define ADC5_AMUX_THM1_400K_PU			0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define ADC5_AMUX_THM2_400K_PU			0x6e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define ADC5_AMUX_THM3_400K_PU			0x6f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define ADC5_AMUX_THM4_400K_PU			0x70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define ADC5_AMUX_THM5_400K_PU			0x71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define ADC5_GPIO1_400K_PU			0x72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define ADC5_GPIO2_400K_PU			0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define ADC5_GPIO3_400K_PU			0x74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ADC5_GPIO4_400K_PU			0x75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define ADC5_GPIO5_400K_PU			0x76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ADC5_GPIO6_400K_PU			0x77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define ADC5_GPIO7_400K_PU			0x78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ADC5_SBUx_400K_PU			0x79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) /* 1/3 Divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define ADC5_GPIO1_DIV3				0x92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define ADC5_GPIO2_DIV3				0x93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define ADC5_GPIO3_DIV3				0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define ADC5_GPIO4_DIV3				0x95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define ADC5_GPIO5_DIV3				0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define ADC5_GPIO6_DIV3				0x97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define ADC5_GPIO7_DIV3				0x98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define ADC5_SBUx_DIV3				0x99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) /* Current and combined current/voltage channels */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define ADC5_INT_EXT_ISENSE			0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define ADC5_PARALLEL_ISENSE			0xa5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define ADC5_CUR_REPLICA_VDS			0xa7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define ADC5_CUR_SENS_BATFET_VDS_OFFSET		0xa9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define ADC5_CUR_SENS_REPLICA_VDS_OFFSET	0xab
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define ADC5_EXT_SENS_OFFSET			0xad
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define ADC5_INT_EXT_ISENSE_VBAT_VDATA		0xb0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define ADC5_INT_EXT_ISENSE_VBAT_IDATA		0xb1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define ADC5_EXT_ISENSE_VBAT_VDATA		0xb2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define ADC5_EXT_ISENSE_VBAT_IDATA		0xb3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define ADC5_PARALLEL_ISENSE_VBAT_VDATA		0xb4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define ADC5_PARALLEL_ISENSE_VBAT_IDATA		0xb5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define ADC5_MAX_CHANNEL			0xc0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) /* ADC channels for ADC for PMIC7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define ADC7_REF_GND				0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ADC7_1P25VREF				0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ADC7_VREF_VADC				0x02
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ADC7_DIE_TEMP				0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ADC7_AMUX_THM1				0x04
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ADC7_AMUX_THM2				0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ADC7_AMUX_THM3				0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ADC7_AMUX_THM4				0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ADC7_AMUX_THM5				0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ADC7_AMUX_THM6				0x09
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ADC7_GPIO1				0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ADC7_GPIO2				0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ADC7_GPIO3				0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ADC7_GPIO4				0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ADC7_CHG_TEMP				0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ADC7_USB_IN_V_16			0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ADC7_VDC_16				0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ADC7_CC1_ID				0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ADC7_VREF_BAT_THERM			0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ADC7_IIN_FB				0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* 30k pull-up1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ADC7_AMUX_THM1_30K_PU			0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ADC7_AMUX_THM2_30K_PU			0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ADC7_AMUX_THM3_30K_PU			0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ADC7_AMUX_THM4_30K_PU			0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ADC7_AMUX_THM5_30K_PU			0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ADC7_AMUX_THM6_30K_PU			0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ADC7_GPIO1_30K_PU			0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ADC7_GPIO2_30K_PU			0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ADC7_GPIO3_30K_PU			0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ADC7_GPIO4_30K_PU			0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ADC7_CC1_ID_30K_PU			0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* 100k pull-up2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define ADC7_AMUX_THM1_100K_PU			0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define ADC7_AMUX_THM2_100K_PU			0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define ADC7_AMUX_THM3_100K_PU			0x46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define ADC7_AMUX_THM4_100K_PU			0x47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define ADC7_AMUX_THM5_100K_PU			0x48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define ADC7_AMUX_THM6_100K_PU			0x49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define ADC7_GPIO1_100K_PU			0x4a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ADC7_GPIO2_100K_PU			0x4b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ADC7_GPIO3_100K_PU			0x4c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define ADC7_GPIO4_100K_PU			0x4d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define ADC7_CC1_ID_100K_PU			0x53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* 400k pull-up3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define ADC7_AMUX_THM1_400K_PU			0x64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ADC7_AMUX_THM2_400K_PU			0x65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define ADC7_AMUX_THM3_400K_PU			0x66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ADC7_AMUX_THM4_400K_PU			0x67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define ADC7_AMUX_THM5_400K_PU			0x68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define ADC7_AMUX_THM6_400K_PU			0x69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define ADC7_GPIO1_400K_PU			0x6a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define ADC7_GPIO2_400K_PU			0x6b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define ADC7_GPIO3_400K_PU			0x6c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define ADC7_GPIO4_400K_PU			0x6d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define ADC7_CC1_ID_400K_PU			0x73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) /* 1/3 Divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define ADC7_GPIO1_DIV3				0x8a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define ADC7_GPIO2_DIV3				0x8b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ADC7_GPIO3_DIV3				0x8c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define ADC7_GPIO4_DIV3				0x8d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ADC7_VPH_PWR				0x8e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define ADC7_VBAT_SNS				0x8f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ADC7_SBUx				0x94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define ADC7_VBAT_2S_MID			0x96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_H */