Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2020, The Linux Foundation. All rights reserved.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #ifndef PM8350_SID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define PM8350_SID					1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* ADC channels for PM8350_ADC for PMIC7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PM8350_ADC7_REF_GND			(PM8350_SID << 8 | 0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PM8350_ADC7_1P25VREF			(PM8350_SID << 8 | 0x01)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PM8350_ADC7_VREF_VADC			(PM8350_SID << 8 | 0x02)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define PM8350_ADC7_DIE_TEMP			(PM8350_SID << 8 | 0x03)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define PM8350_ADC7_AMUX_THM1			(PM8350_SID << 8 | 0x04)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define PM8350_ADC7_AMUX_THM2			(PM8350_SID << 8 | 0x05)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define PM8350_ADC7_AMUX_THM3			(PM8350_SID << 8 | 0x06)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define PM8350_ADC7_AMUX_THM4			(PM8350_SID << 8 | 0x07)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define PM8350_ADC7_AMUX_THM5			(PM8350_SID << 8 | 0x08)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define PM8350_ADC7_GPIO1			(PM8350_SID << 8 | 0x0a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PM8350_ADC7_GPIO2			(PM8350_SID << 8 | 0x0b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define PM8350_ADC7_GPIO3			(PM8350_SID << 8 | 0x0c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define PM8350_ADC7_GPIO4			(PM8350_SID << 8 | 0x0d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* 30k pull-up1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PM8350_ADC7_AMUX_THM1_30K_PU		(PM8350_SID << 8 | 0x24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define PM8350_ADC7_AMUX_THM2_30K_PU		(PM8350_SID << 8 | 0x25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define PM8350_ADC7_AMUX_THM3_30K_PU		(PM8350_SID << 8 | 0x26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define PM8350_ADC7_AMUX_THM4_30K_PU		(PM8350_SID << 8 | 0x27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define PM8350_ADC7_AMUX_THM5_30K_PU		(PM8350_SID << 8 | 0x28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PM8350_ADC7_GPIO1_30K_PU		(PM8350_SID << 8 | 0x2a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PM8350_ADC7_GPIO2_30K_PU		(PM8350_SID << 8 | 0x2b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PM8350_ADC7_GPIO3_30K_PU		(PM8350_SID << 8 | 0x2c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PM8350_ADC7_GPIO4_30K_PU		(PM8350_SID << 8 | 0x2d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* 100k pull-up2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PM8350_ADC7_AMUX_THM1_100K_PU		(PM8350_SID << 8 | 0x44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PM8350_ADC7_AMUX_THM2_100K_PU		(PM8350_SID << 8 | 0x45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PM8350_ADC7_AMUX_THM3_100K_PU		(PM8350_SID << 8 | 0x46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PM8350_ADC7_AMUX_THM4_100K_PU		(PM8350_SID << 8 | 0x47)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PM8350_ADC7_AMUX_THM5_100K_PU		(PM8350_SID << 8 | 0x48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PM8350_ADC7_GPIO1_100K_PU		(PM8350_SID << 8 | 0x4a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PM8350_ADC7_GPIO2_100K_PU		(PM8350_SID << 8 | 0x4b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PM8350_ADC7_GPIO3_100K_PU		(PM8350_SID << 8 | 0x4c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PM8350_ADC7_GPIO4_100K_PU		(PM8350_SID << 8 | 0x4d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* 400k pull-up3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PM8350_ADC7_AMUX_THM1_400K_PU		(PM8350_SID << 8 | 0x64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PM8350_ADC7_AMUX_THM2_400K_PU		(PM8350_SID << 8 | 0x65)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PM8350_ADC7_AMUX_THM3_400K_PU		(PM8350_SID << 8 | 0x66)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PM8350_ADC7_AMUX_THM4_400K_PU		(PM8350_SID << 8 | 0x67)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PM8350_ADC7_AMUX_THM5_400K_PU		(PM8350_SID << 8 | 0x68)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PM8350_ADC7_GPIO1_400K_PU		(PM8350_SID << 8 | 0x6a)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PM8350_ADC7_GPIO2_400K_PU		(PM8350_SID << 8 | 0x6b)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PM8350_ADC7_GPIO3_400K_PU		(PM8350_SID << 8 | 0x6c)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PM8350_ADC7_GPIO4_400K_PU		(PM8350_SID << 8 | 0x6d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* 1/3 Divider */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PM8350_ADC7_GPIO4_DIV3			(PM8350_SID << 8 | 0x8d)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PM8350_ADC7_VPH_PWR			(PM8350_SID << 8 | 0x8e)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #endif /* _DT_BINDINGS_QCOM_SPMI_VADC_PM8350_H */