Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * This header provides constants for binding nvidia,tegra194-gpio*.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * The first cell in Tegra's GPIO specifier is the GPIO ID. The macros below
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * provide names for this.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * The second cell contains standard flag values specified in gpio.h.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #ifndef _DT_BINDINGS_GPIO_TEGRA194_GPIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define _DT_BINDINGS_GPIO_TEGRA194_GPIO_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #include <dt-bindings/gpio/gpio.h>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* GPIOs implemented by main GPIO controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA194_MAIN_GPIO_PORT_A 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA194_MAIN_GPIO_PORT_B 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA194_MAIN_GPIO_PORT_C 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA194_MAIN_GPIO_PORT_D 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA194_MAIN_GPIO_PORT_E 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA194_MAIN_GPIO_PORT_F 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA194_MAIN_GPIO_PORT_G 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA194_MAIN_GPIO_PORT_H 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA194_MAIN_GPIO_PORT_I 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA194_MAIN_GPIO_PORT_J 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA194_MAIN_GPIO_PORT_K 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA194_MAIN_GPIO_PORT_L 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA194_MAIN_GPIO_PORT_M 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA194_MAIN_GPIO_PORT_N 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA194_MAIN_GPIO_PORT_O 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA194_MAIN_GPIO_PORT_P 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA194_MAIN_GPIO_PORT_Q 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA194_MAIN_GPIO_PORT_R 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA194_MAIN_GPIO_PORT_S 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA194_MAIN_GPIO_PORT_T 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA194_MAIN_GPIO_PORT_U 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA194_MAIN_GPIO_PORT_V 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA194_MAIN_GPIO_PORT_W 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA194_MAIN_GPIO_PORT_X 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA194_MAIN_GPIO_PORT_Y 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA194_MAIN_GPIO_PORT_Z 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA194_MAIN_GPIO_PORT_FF 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA194_MAIN_GPIO_PORT_GG 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA194_MAIN_GPIO(port, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 	((TEGRA194_MAIN_GPIO_PORT_##port * 8) + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* GPIOs implemented by AON GPIO controller */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA194_AON_GPIO_PORT_AA 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA194_AON_GPIO_PORT_BB 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA194_AON_GPIO_PORT_CC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA194_AON_GPIO_PORT_DD 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEGRA194_AON_GPIO_PORT_EE 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA194_AON_GPIO(port, offset) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) 	((TEGRA194_AON_GPIO_PORT_##port * 8) + offset)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #endif