^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Bibby Hsieh <bibby.hsieh@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DT_BINDINGS_GCE_MT8183_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DT_BINDINGS_GCE_MT8183_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CMDQ_NO_TIMEOUT 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* GCE HW thread priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CMDQ_THR_PRIO_LOWEST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CMDQ_THR_PRIO_HIGHEST 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) /* GCE SUBSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SUBSYS_1300XXXX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SUBSYS_1400XXXX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SUBSYS_1401XXXX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SUBSYS_1402XXXX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SUBSYS_1502XXXX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SUBSYS_1880XXXX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SUBSYS_1881XXXX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUBSYS_1882XXXX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SUBSYS_1883XXXX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SUBSYS_1884XXXX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUBSYS_1000XXXX 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUBSYS_1001XXXX 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SUBSYS_1002XXXX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SUBSYS_1003XXXX 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUBSYS_1004XXXX 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUBSYS_1005XXXX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUBSYS_1020XXXX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUBSYS_1028XXXX 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUBSYS_1700XXXX 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUBSYS_1701XXXX 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SUBSYS_1702XXXX 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUBSYS_1703XXXX 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUBSYS_1800XXXX 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SUBSYS_1801XXXX 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUBSYS_1802XXXX 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUBSYS_1804XXXX 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUBSYS_1805XXXX 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUBSYS_1808XXXX 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUBSYS_180aXXXX 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUBSYS_180bXXXX 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CMDQ_EVENT_DISP_RDMA0_SOF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CMDQ_EVENT_DISP_RDMA1_SOF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CMDQ_EVENT_MDP_RDMA0_SOF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CMDQ_EVENT_MDP_RSZ0_SOF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CMDQ_EVENT_MDP_RSZ1_SOF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CMDQ_EVENT_MDP_TDSHP_SOF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CMDQ_EVENT_MDP_WROT0_SOF 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CMDQ_EVENT_MDP_WDMA0_SOF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CMDQ_EVENT_DISP_OVL0_SOF 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CMDQ_EVENT_DISP_OVL0_2L_SOF 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CMDQ_EVENT_DISP_OVL1_2L_SOF 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CMDQ_EVENT_DISP_WDMA0_SOF 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CMDQ_EVENT_DISP_COLOR0_SOF 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CMDQ_EVENT_DISP_CCORR0_SOF 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CMDQ_EVENT_DISP_AAL0_SOF 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CMDQ_EVENT_DISP_GAMMA0_SOF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CMDQ_EVENT_DISP_DITHER0_SOF 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CMDQ_EVENT_DISP_PWM0_SOF 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CMDQ_EVENT_DISP_DSI0_SOF 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CMDQ_EVENT_DISP_DPI0_SOF 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CMDQ_EVENT_DISP_RSZ_SOF 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CMDQ_EVENT_MDP_AAL_SOF 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CMDQ_EVENT_MDP_CCORR_SOF 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CMDQ_EVENT_DISP_DBI_SOF 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CMDQ_EVENT_DISP_RDMA0_EOF 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CMDQ_EVENT_DISP_RDMA1_EOF 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CMDQ_EVENT_MDP_RDMA0_EOF 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CMDQ_EVENT_MDP_RSZ0_EOF 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CMDQ_EVENT_MDP_RSZ1_EOF 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CMDQ_EVENT_MDP_TDSHP_EOF 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CMDQ_EVENT_MDP_WROT0_EOF 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CMDQ_EVENT_MDP_WDMA0_EOF 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CMDQ_EVENT_DISP_OVL0_EOF 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CMDQ_EVENT_DISP_OVL0_2L_EOF 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CMDQ_EVENT_DISP_OVL1_2L_EOF 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CMDQ_EVENT_DISP_WDMA0_EOF 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CMDQ_EVENT_DISP_COLOR0_EOF 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CMDQ_EVENT_DISP_CCORR0_EOF 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CMDQ_EVENT_DISP_AAL0_EOF 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CMDQ_EVENT_DISP_GAMMA0_EOF 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CMDQ_EVENT_DISP_DITHER0_EOF 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CMDQ_EVENT_DSI0_EOF 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CMDQ_EVENT_DPI0_EOF 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CMDQ_EVENT_DISP_RSZ_EOF 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CMDQ_EVENT_MDP_AAL_EOF 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CMDQ_EVENT_MDP_CCORR_EOF 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CMDQ_EVENT_DBI_EOF 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CMDQ_EVENT_MUTEX_STREAM_DONE0 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CMDQ_EVENT_MUTEX_STREAM_DONE1 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CMDQ_EVENT_MUTEX_STREAM_DONE2 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CMDQ_EVENT_MUTEX_STREAM_DONE3 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CMDQ_EVENT_MUTEX_STREAM_DONE4 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CMDQ_EVENT_MUTEX_STREAM_DONE5 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CMDQ_EVENT_MUTEX_STREAM_DONE6 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CMDQ_EVENT_MUTEX_STREAM_DONE7 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CMDQ_EVENT_MUTEX_STREAM_DONE8 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CMDQ_EVENT_MUTEX_STREAM_DONE9 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CMDQ_EVENT_MUTEX_STREAM_DONE10 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CMDQ_EVENT_MUTEX_STREAM_DONE11 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CMDQ_EVENT_DISP_RDMA0_BUF_UNDERRUN_EVEN 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CMDQ_EVENT_DISP_RDMA1_BUF_UNDERRUN_EVEN 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CMDQ_EVENT_DSI0_TE_EVENT 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CMDQ_EVENT_DSI0_IRQ_EVENT 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CMDQ_EVENT_DSI0_DONE_EVENT 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CMDQ_EVENT_DISP_WDMA0_SW_RST_DONE 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CMDQ_EVENT_MDP_WDMA_SW_RST_DONE 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CMDQ_EVENT_MDP_WROT0_SW_RST_DONE 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CMDQ_EVENT_MDP_RDMA0_SW_RST_DONE 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CMDQ_EVENT_DISP_OVL0_FRAME_RST_DONE_PULE 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CMDQ_EVENT_DISP_OVL0_2L_FRAME_RST_DONE_ULSE 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CMDQ_EVENT_DISP_OVL1_2L_FRAME_RST_DONE_ULSE 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_0 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_1 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_2 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_3 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_4 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_5 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_6 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_7 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_8 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_9 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_10 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_11 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_12 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_13 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_14 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_15 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_16 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_17 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CMDQ_EVENT_ISP_FRAME_DONE_P2_18 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CMDQ_EVENT_AMD_FRAME_DONE 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CMDQ_EVENT_DVE_DONE 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CMDQ_EVENT_WMFE_DONE 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CMDQ_EVENT_RSC_DONE 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CMDQ_EVENT_MFB_DONE 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CMDQ_EVENT_WPE_A_DONE 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CMDQ_EVENT_SPE_B_DONE 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CMDQ_EVENT_OCC_DONE 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CMDQ_EVENT_VENC_CMDQ_FRAME_DONE 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CMDQ_EVENT_JPG_ENC_CMDQ_DONE 290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CMDQ_EVENT_JPG_DEC_CMDQ_DONE 291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CMDQ_EVENT_VENC_CMDQ_MB_DONE 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CMDQ_EVENT_VENC_CMDQ_128BYTE_DONE 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CMDQ_EVENT_ISP_FRAME_DONE_A 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CMDQ_EVENT_ISP_FRAME_DONE_B 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CMDQ_EVENT_CAMSV0_PASS1_DONE 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CMDQ_EVENT_CAMSV1_PASS1_DONE 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CMDQ_EVENT_CAMSV2_PASS1_DONE 325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CMDQ_EVENT_TSF_DONE 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CMDQ_EVENT_SENINF_CAM0_FIFO_FULL 327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CMDQ_EVENT_SENINF_CAM1_FIFO_FULL 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CMDQ_EVENT_SENINF_CAM2_FIFO_FULL 329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CMDQ_EVENT_SENINF_CAM3_FIFO_FULL 330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CMDQ_EVENT_SENINF_CAM4_FIFO_FULL 331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CMDQ_EVENT_SENINF_CAM5_FIFO_FULL 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CMDQ_EVENT_SENINF_CAM6_FIFO_FULL 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CMDQ_EVENT_SENINF_CAM7_FIFO_FULL 334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CMDQ_EVENT_IPU_CORE0_DONE0 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CMDQ_EVENT_IPU_CORE0_DONE1 354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CMDQ_EVENT_IPU_CORE0_DONE2 355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CMDQ_EVENT_IPU_CORE0_DONE3 356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CMDQ_EVENT_IPU_CORE1_DONE0 385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CMDQ_EVENT_IPU_CORE1_DONE1 386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CMDQ_EVENT_IPU_CORE1_DONE2 387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CMDQ_EVENT_IPU_CORE1_DONE3 388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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