Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2018 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * Author: Houlong Wei <houlong.wei@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _DT_BINDINGS_GCE_MT8173_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _DT_BINDINGS_GCE_MT8173_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* GCE HW thread priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CMDQ_THR_PRIO_LOWEST	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CMDQ_THR_PRIO_HIGHEST	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* GCE SUBSYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SUBSYS_1400XXXX		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SUBSYS_1401XXXX		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SUBSYS_1402XXXX		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) /* GCE HW EVENT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CMDQ_EVENT_DISP_OVL0_SOF		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CMDQ_EVENT_DISP_OVL1_SOF		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CMDQ_EVENT_DISP_RDMA0_SOF		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CMDQ_EVENT_DISP_RDMA1_SOF		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CMDQ_EVENT_DISP_RDMA2_SOF		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CMDQ_EVENT_DISP_WDMA0_SOF		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CMDQ_EVENT_DISP_WDMA1_SOF		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CMDQ_EVENT_DISP_OVL0_EOF		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CMDQ_EVENT_DISP_OVL1_EOF		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CMDQ_EVENT_DISP_RDMA0_EOF		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CMDQ_EVENT_DISP_RDMA1_EOF		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CMDQ_EVENT_DISP_RDMA2_EOF		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CMDQ_EVENT_DISP_WDMA0_EOF		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CMDQ_EVENT_DISP_WDMA1_EOF		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CMDQ_EVENT_MUTEX0_STREAM_EOF		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CMDQ_EVENT_MUTEX1_STREAM_EOF		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CMDQ_EVENT_MUTEX2_STREAM_EOF		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CMDQ_EVENT_MUTEX3_STREAM_EOF		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CMDQ_EVENT_MUTEX4_STREAM_EOF		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #endif