^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 MediaTek Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Dennis-YC Hsieh <dennis-yc.hsieh@mediatek.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_GCE_MT6779_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_GCE_MT6779_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CMDQ_NO_TIMEOUT 0xffffffff
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* GCE HW thread priority */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CMDQ_THR_PRIO_LOWEST 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CMDQ_THR_PRIO_1 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CMDQ_THR_PRIO_2 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CMDQ_THR_PRIO_3 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CMDQ_THR_PRIO_4 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CMDQ_THR_PRIO_5 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CMDQ_THR_PRIO_6 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CMDQ_THR_PRIO_HIGHEST 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* GCE subsys table */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SUBSYS_1300XXXX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SUBSYS_1400XXXX 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SUBSYS_1401XXXX 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SUBSYS_1402XXXX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SUBSYS_1502XXXX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SUBSYS_1880XXXX 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define SUBSYS_1881XXXX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SUBSYS_1882XXXX 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SUBSYS_1883XXXX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SUBSYS_1884XXXX 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SUBSYS_1000XXXX 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SUBSYS_1001XXXX 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SUBSYS_1002XXXX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SUBSYS_1003XXXX 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SUBSYS_1004XXXX 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SUBSYS_1005XXXX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SUBSYS_1020XXXX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define SUBSYS_1028XXXX 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define SUBSYS_1700XXXX 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SUBSYS_1701XXXX 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SUBSYS_1702XXXX 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SUBSYS_1703XXXX 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SUBSYS_1800XXXX 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SUBSYS_1801XXXX 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SUBSYS_1802XXXX 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SUBSYS_1804XXXX 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SUBSYS_1805XXXX 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SUBSYS_1808XXXX 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SUBSYS_180aXXXX 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SUBSYS_180bXXXX 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CMDQ_SUBSYS_OFF 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* GCE hardware events */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CMDQ_EVENT_DISP_RDMA0_SOF 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CMDQ_EVENT_DISP_RDMA1_SOF 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CMDQ_EVENT_MDP_RDMA0_SOF 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CMDQ_EVENT_MDP_RDMA1_SOF 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CMDQ_EVENT_MDP_RSZ0_SOF 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CMDQ_EVENT_MDP_RSZ1_SOF 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CMDQ_EVENT_MDP_TDSHP_SOF 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CMDQ_EVENT_MDP_WROT0_SOF 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CMDQ_EVENT_MDP_WROT1_SOF 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CMDQ_EVENT_DISP_OVL0_SOF 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CMDQ_EVENT_DISP_2L_OVL0_SOF 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CMDQ_EVENT_DISP_2L_OVL1_SOF 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CMDQ_EVENT_DISP_WDMA0_SOF 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CMDQ_EVENT_DISP_COLOR0_SOF 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CMDQ_EVENT_DISP_CCORR0_SOF 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CMDQ_EVENT_DISP_AAL0_SOF 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CMDQ_EVENT_DISP_GAMMA0_SOF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CMDQ_EVENT_DISP_DITHER0_SOF 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CMDQ_EVENT_DISP_PWM0_SOF 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CMDQ_EVENT_DISP_DSI0_SOF 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CMDQ_EVENT_DISP_DPI0_SOF 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CMDQ_EVENT_DISP_POSTMASK0_SOF 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CMDQ_EVENT_DISP_RSZ0_SOF 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CMDQ_EVENT_MDP_AAL_SOF 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CMDQ_EVENT_MDP_CCORR_SOF 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CMDQ_EVENT_DISP_DBI0_SOF 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CMDQ_EVENT_ISP_RELAY_SOF 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CMDQ_EVENT_IPU_RELAY_SOF 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CMDQ_EVENT_DISP_RDMA0_EOF 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CMDQ_EVENT_DISP_RDMA1_EOF 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CMDQ_EVENT_MDP_RDMA0_EOF 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CMDQ_EVENT_MDP_RDMA1_EOF 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CMDQ_EVENT_MDP_RSZ0_EOF 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CMDQ_EVENT_MDP_RSZ1_EOF 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CMDQ_EVENT_MDP_TDSHP_EOF 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CMDQ_EVENT_MDP_WROT0_W_EOF 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CMDQ_EVENT_MDP_WROT1_W_EOF 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CMDQ_EVENT_DISP_OVL0_EOF 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CMDQ_EVENT_DISP_2L_OVL0_EOF 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CMDQ_EVENT_DISP_2L_OVL1_EOF 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CMDQ_EVENT_DISP_WDMA0_EOF 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CMDQ_EVENT_DISP_COLOR0_EOF 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CMDQ_EVENT_DISP_CCORR0_EOF 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CMDQ_EVENT_DISP_AAL0_EOF 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CMDQ_EVENT_DISP_GAMMA0_EOF 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CMDQ_EVENT_DISP_DITHER0_EOF 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CMDQ_EVENT_DISP_DSI0_EOF 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CMDQ_EVENT_DISP_DPI0_EOF 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CMDQ_EVENT_DISP_RSZ0_EOF 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CMDQ_EVENT_MDP_AAL_FRAME_DONE 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CMDQ_EVENT_MDP_CCORR_FRAME_DONE 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CMDQ_EVENT_DISP_POSTMASK0_FRAME_DONE 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CMDQ_EVENT_MUTEX0_STREAM_EOF 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CMDQ_EVENT_MUTEX1_STREAM_EOF 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CMDQ_EVENT_MUTEX2_STREAM_EOF 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CMDQ_EVENT_MUTEX3_STREAM_EOF 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CMDQ_EVENT_MUTEX4_STREAM_EOF 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CMDQ_EVENT_MUTEX5_STREAM_EOF 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CMDQ_EVENT_MUTEX6_STREAM_EOF 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CMDQ_EVENT_MUTEX7_STREAM_EOF 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CMDQ_EVENT_MUTEX8_STREAM_EOF 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CMDQ_EVENT_MUTEX9_STREAM_EOF 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CMDQ_EVENT_MUTEX10_STREAM_EOF 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CMDQ_EVENT_MUTEX11_STREAM_EOF 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CMDQ_EVENT_DISP_RDMA0_UNDERRUN 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CMDQ_EVENT_DISP_RDMA1_UNDERRUN 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CMDQ_EVENT_DISP_RDMA2_UNDERRUN 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CMDQ_EVENT_DISP_RDMA3_UNDERRUN 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CMDQ_EVENT_DSI0_TE 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CMDQ_EVENT_DSI0_IRQ_EVENT 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CMDQ_EVENT_DSI0_DONE_EVENT 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CMDQ_EVENT_DISP_POSTMASK0_RST_DONE 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CMDQ_EVENT_DISP_WDMA0_RST_DONE 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CMDQ_EVENT_MDP_WROT0_RST_DONE 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CMDQ_EVENT_MDP_RDMA0_RST_DONE 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CMDQ_EVENT_DISP_OVL0_RST_DONE 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CMDQ_EVENT_DISP_OVL0_2L_RST_DONE 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CMDQ_EVENT_DISP_OVL1_2L_RST_DONE 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CMDQ_EVENT_DIP_CQ_THREAD0_EOF 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CMDQ_EVENT_DIP_CQ_THREAD1_EOF 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CMDQ_EVENT_DIP_CQ_THREAD2_EOF 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CMDQ_EVENT_DIP_CQ_THREAD3_EOF 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CMDQ_EVENT_DIP_CQ_THREAD4_EOF 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CMDQ_EVENT_DIP_CQ_THREAD5_EOF 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CMDQ_EVENT_DIP_CQ_THREAD6_EOF 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CMDQ_EVENT_DIP_CQ_THREAD7_EOF 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CMDQ_EVENT_DIP_CQ_THREAD8_EOF 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CMDQ_EVENT_DIP_CQ_THREAD9_EOF 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CMDQ_EVENT_DIP_CQ_THREAD10_EOF 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CMDQ_EVENT_DIP_CQ_THREAD11_EOF 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CMDQ_EVENT_DIP_CQ_THREAD12_EOF 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CMDQ_EVENT_DIP_CQ_THREAD13_EOF 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CMDQ_EVENT_DIP_CQ_THREAD14_EOF 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CMDQ_EVENT_DIP_CQ_THREAD15_EOF 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CMDQ_EVENT_DIP_CQ_THREAD16_EOF 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CMDQ_EVENT_DIP_CQ_THREAD17_EOF 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CMDQ_EVENT_DIP_CQ_THREAD18_EOF 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CMDQ_EVENT_DIP_DMA_ERR_EVENT 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CMDQ_EVENT_AMD_FRAME_DONE 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CMDQ_EVENT_MFB_DONE 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CMDQ_EVENT_WPE_A_EOF 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CMDQ_EVENT_VENC_EOF 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CMDQ_EVENT_VENC_CMDQ_PAUSE_DONE 290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CMDQ_EVENT_JPEG_ENC_EOF 291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CMDQ_EVENT_VENC_MB_DONE 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CMDQ_EVENT_VENC_128BYTE_CNT_DONE 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CMDQ_EVENT_ISP_FRAME_DONE_A 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CMDQ_EVENT_ISP_FRAME_DONE_B 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CMDQ_EVENT_ISP_FRAME_DONE_C 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CMDQ_EVENT_ISP_CAMSV_0_PASS1_DONE 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CMDQ_EVENT_ISP_CAMSV_0_2_PASS1_DONE 325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CMDQ_EVENT_ISP_CAMSV_1_PASS1_DONE 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CMDQ_EVENT_ISP_CAMSV_2_PASS1_DONE 327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CMDQ_EVENT_ISP_CAMSV_3_PASS1_DONE 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CMDQ_EVENT_ISP_TSF_DONE 329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CMDQ_EVENT_SENINF_0_FIFO_FULL 330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CMDQ_EVENT_SENINF_1_FIFO_FULL 331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CMDQ_EVENT_SENINF_2_FIFO_FULL 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CMDQ_EVENT_SENINF_3_FIFO_FULL 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CMDQ_EVENT_SENINF_4_FIFO_FULL 334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CMDQ_EVENT_SENINF_5_FIFO_FULL 335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CMDQ_EVENT_SENINF_6_FIFO_FULL 336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CMDQ_EVENT_SENINF_7_FIFO_FULL 337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CMDQ_EVENT_TG_OVRUN_A_INT_DLY 338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CMDQ_EVENT_TG_OVRUN_B_INT_DLY 339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CMDQ_EVENT_TG_OVRUN_C_INT 340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CMDQ_EVENT_TG_GRABERR_A_INT_DLY 341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CMDQ_EVENT_TG_GRABERR_B_INT_DLY 342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CMDQ_EVENT_TG_GRABERR_C_INT 343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CMDQ_EVENT_CQ_VR_SNAP_A_INT_DLY 344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CMDQ_EVENT_CQ_VR_SNAP_B_INT_DLY 345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CMDQ_EVENT_CQ_VR_SNAP_C_INT 346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CMDQ_EVENT_DMA_R1_ERROR_A_INT_DLY 347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CMDQ_EVENT_DMA_R1_ERROR_B_INT_DLY 348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CMDQ_EVENT_DMA_R1_ERROR_C_INT 349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_0 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_1 354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_2 355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CMDQ_EVENT_APU_GCE_CORE0_EVENT_3 356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_0 385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_1 386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_2 387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CMDQ_EVENT_APU_GCE_CORE1_EVENT_3 388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CMDQ_EVENT_VDEC_EVENT_0 416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CMDQ_EVENT_VDEC_EVENT_1 417
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CMDQ_EVENT_VDEC_EVENT_2 418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CMDQ_EVENT_VDEC_EVENT_3 419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CMDQ_EVENT_VDEC_EVENT_4 420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CMDQ_EVENT_VDEC_EVENT_5 421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CMDQ_EVENT_VDEC_EVENT_6 422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CMDQ_EVENT_VDEC_EVENT_7 423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CMDQ_EVENT_VDEC_EVENT_8 424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CMDQ_EVENT_VDEC_EVENT_9 425
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CMDQ_EVENT_VDEC_EVENT_10 426
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CMDQ_EVENT_VDEC_EVENT_11 427
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CMDQ_EVENT_VDEC_EVENT_12 428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CMDQ_EVENT_VDEC_EVENT_13 429
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CMDQ_EVENT_VDEC_EVENT_14 430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CMDQ_EVENT_VDEC_EVENT_15 431
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CMDQ_EVENT_FDVT_DONE 449
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CMDQ_EVENT_FE_DONE 450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CMDQ_EVENT_RSC_EOF 451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CMDQ_EVENT_DVS_DONE_ASYNC_SHOT 452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CMDQ_EVENT_DVP_DONE_ASYNC_SHOT 453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CMDQ_EVENT_DSI0_TE_INFRA 898
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags