^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0+ */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2016 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright 2017-2018 NXP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __DT_BINDINGS_RSCRC_IMX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __DT_BINDINGS_RSCRC_IMX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * These defines are used to indicate a resource. Resources include peripherals
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * and bus masters (but not memory regions). Note items from list should
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * never be changed or removed (only added to at the end of the list).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define IMX_SC_R_A53 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IMX_SC_R_A53_0 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define IMX_SC_R_A53_1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define IMX_SC_R_A53_2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define IMX_SC_R_A53_3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define IMX_SC_R_A72 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define IMX_SC_R_A72_0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define IMX_SC_R_A72_1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define IMX_SC_R_A72_2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define IMX_SC_R_A72_3 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define IMX_SC_R_CCI 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define IMX_SC_R_DB 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define IMX_SC_R_DRC_0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define IMX_SC_R_DRC_1 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define IMX_SC_R_GIC_SMMU 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define IMX_SC_R_IRQSTR_M4_0 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define IMX_SC_R_IRQSTR_M4_1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define IMX_SC_R_SMMU 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define IMX_SC_R_GIC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define IMX_SC_R_DC_0_BLIT0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define IMX_SC_R_DC_0_BLIT1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define IMX_SC_R_DC_0_BLIT2 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define IMX_SC_R_DC_0_BLIT_OUT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define IMX_SC_R_PERF 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define IMX_SC_R_DC_0_WARP 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define IMX_SC_R_DC_0_VIDEO0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define IMX_SC_R_DC_0_VIDEO1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define IMX_SC_R_DC_0_FRAC0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define IMX_SC_R_DC_0 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define IMX_SC_R_GPU_2_PID0 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define IMX_SC_R_DC_0_PLL_0 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define IMX_SC_R_DC_0_PLL_1 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define IMX_SC_R_DC_1_BLIT0 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define IMX_SC_R_DC_1_BLIT1 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define IMX_SC_R_DC_1_BLIT2 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define IMX_SC_R_DC_1_BLIT_OUT 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define IMX_SC_R_DC_1_WARP 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define IMX_SC_R_DC_1_VIDEO0 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IMX_SC_R_DC_1_VIDEO1 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define IMX_SC_R_DC_1_FRAC0 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define IMX_SC_R_DC_1 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define IMX_SC_R_DC_1_PLL_0 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define IMX_SC_R_DC_1_PLL_1 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define IMX_SC_R_SPI_0 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define IMX_SC_R_SPI_1 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define IMX_SC_R_SPI_2 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define IMX_SC_R_SPI_3 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define IMX_SC_R_UART_0 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define IMX_SC_R_UART_1 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define IMX_SC_R_UART_2 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define IMX_SC_R_UART_3 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define IMX_SC_R_UART_4 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define IMX_SC_R_EMVSIM_0 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define IMX_SC_R_EMVSIM_1 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define IMX_SC_R_DMA_0_CH0 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define IMX_SC_R_DMA_0_CH1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define IMX_SC_R_DMA_0_CH2 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define IMX_SC_R_DMA_0_CH3 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define IMX_SC_R_DMA_0_CH4 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define IMX_SC_R_DMA_0_CH5 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define IMX_SC_R_DMA_0_CH6 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define IMX_SC_R_DMA_0_CH7 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define IMX_SC_R_DMA_0_CH8 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define IMX_SC_R_DMA_0_CH9 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define IMX_SC_R_DMA_0_CH10 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define IMX_SC_R_DMA_0_CH11 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define IMX_SC_R_DMA_0_CH12 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define IMX_SC_R_DMA_0_CH13 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define IMX_SC_R_DMA_0_CH14 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define IMX_SC_R_DMA_0_CH15 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define IMX_SC_R_DMA_0_CH16 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define IMX_SC_R_DMA_0_CH17 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IMX_SC_R_DMA_0_CH18 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IMX_SC_R_DMA_0_CH19 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IMX_SC_R_DMA_0_CH20 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IMX_SC_R_DMA_0_CH21 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IMX_SC_R_DMA_0_CH22 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define IMX_SC_R_DMA_0_CH23 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define IMX_SC_R_DMA_0_CH24 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define IMX_SC_R_DMA_0_CH25 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define IMX_SC_R_DMA_0_CH26 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define IMX_SC_R_DMA_0_CH27 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define IMX_SC_R_DMA_0_CH28 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define IMX_SC_R_DMA_0_CH29 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define IMX_SC_R_DMA_0_CH30 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define IMX_SC_R_DMA_0_CH31 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define IMX_SC_R_I2C_0 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define IMX_SC_R_I2C_1 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define IMX_SC_R_I2C_2 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define IMX_SC_R_I2C_3 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define IMX_SC_R_I2C_4 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define IMX_SC_R_ADC_0 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define IMX_SC_R_ADC_1 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define IMX_SC_R_FTM_0 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define IMX_SC_R_FTM_1 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define IMX_SC_R_CAN_0 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define IMX_SC_R_CAN_1 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define IMX_SC_R_CAN_2 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define IMX_SC_R_DMA_1_CH0 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define IMX_SC_R_DMA_1_CH1 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define IMX_SC_R_DMA_1_CH2 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define IMX_SC_R_DMA_1_CH3 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define IMX_SC_R_DMA_1_CH4 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define IMX_SC_R_DMA_1_CH5 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define IMX_SC_R_DMA_1_CH6 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define IMX_SC_R_DMA_1_CH7 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define IMX_SC_R_DMA_1_CH8 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define IMX_SC_R_DMA_1_CH9 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define IMX_SC_R_DMA_1_CH10 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define IMX_SC_R_DMA_1_CH11 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define IMX_SC_R_DMA_1_CH12 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define IMX_SC_R_DMA_1_CH13 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define IMX_SC_R_DMA_1_CH14 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define IMX_SC_R_DMA_1_CH15 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define IMX_SC_R_DMA_1_CH16 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define IMX_SC_R_DMA_1_CH17 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define IMX_SC_R_DMA_1_CH18 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define IMX_SC_R_DMA_1_CH19 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define IMX_SC_R_DMA_1_CH20 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define IMX_SC_R_DMA_1_CH21 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define IMX_SC_R_DMA_1_CH22 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define IMX_SC_R_DMA_1_CH23 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define IMX_SC_R_DMA_1_CH24 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define IMX_SC_R_DMA_1_CH25 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define IMX_SC_R_DMA_1_CH26 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define IMX_SC_R_DMA_1_CH27 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define IMX_SC_R_DMA_1_CH28 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define IMX_SC_R_DMA_1_CH29 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define IMX_SC_R_DMA_1_CH30 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define IMX_SC_R_DMA_1_CH31 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define IMX_SC_R_UNUSED1 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define IMX_SC_R_UNUSED2 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define IMX_SC_R_UNUSED3 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define IMX_SC_R_UNUSED4 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define IMX_SC_R_GPU_0_PID0 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define IMX_SC_R_GPU_0_PID1 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define IMX_SC_R_GPU_0_PID2 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define IMX_SC_R_GPU_0_PID3 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define IMX_SC_R_GPU_1_PID0 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define IMX_SC_R_GPU_1_PID1 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define IMX_SC_R_GPU_1_PID2 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define IMX_SC_R_GPU_1_PID3 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define IMX_SC_R_PCIE_A 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define IMX_SC_R_SERDES_0 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define IMX_SC_R_MATCH_0 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define IMX_SC_R_MATCH_1 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define IMX_SC_R_MATCH_2 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define IMX_SC_R_MATCH_3 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define IMX_SC_R_MATCH_4 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define IMX_SC_R_MATCH_5 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define IMX_SC_R_MATCH_6 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define IMX_SC_R_MATCH_7 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define IMX_SC_R_MATCH_8 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define IMX_SC_R_MATCH_9 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define IMX_SC_R_MATCH_10 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define IMX_SC_R_MATCH_11 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define IMX_SC_R_MATCH_12 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define IMX_SC_R_MATCH_13 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define IMX_SC_R_MATCH_14 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define IMX_SC_R_PCIE_B 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define IMX_SC_R_SATA_0 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define IMX_SC_R_SERDES_1 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define IMX_SC_R_HSIO_GPIO 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define IMX_SC_R_MATCH_15 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define IMX_SC_R_MATCH_16 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define IMX_SC_R_MATCH_17 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define IMX_SC_R_MATCH_18 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define IMX_SC_R_MATCH_19 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define IMX_SC_R_MATCH_20 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define IMX_SC_R_MATCH_21 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define IMX_SC_R_MATCH_22 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define IMX_SC_R_MATCH_23 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define IMX_SC_R_MATCH_24 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define IMX_SC_R_MATCH_25 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define IMX_SC_R_MATCH_26 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define IMX_SC_R_MATCH_27 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define IMX_SC_R_MATCH_28 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define IMX_SC_R_LCD_0 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define IMX_SC_R_LCD_0_PWM_0 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define IMX_SC_R_LCD_0_I2C_0 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define IMX_SC_R_LCD_0_I2C_1 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define IMX_SC_R_PWM_0 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define IMX_SC_R_PWM_1 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define IMX_SC_R_PWM_2 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define IMX_SC_R_PWM_3 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define IMX_SC_R_PWM_4 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define IMX_SC_R_PWM_5 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define IMX_SC_R_PWM_6 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define IMX_SC_R_PWM_7 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define IMX_SC_R_GPIO_0 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define IMX_SC_R_GPIO_1 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define IMX_SC_R_GPIO_2 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define IMX_SC_R_GPIO_3 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define IMX_SC_R_GPIO_4 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define IMX_SC_R_GPIO_5 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define IMX_SC_R_GPIO_6 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define IMX_SC_R_GPIO_7 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define IMX_SC_R_GPT_0 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define IMX_SC_R_GPT_1 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define IMX_SC_R_GPT_2 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define IMX_SC_R_GPT_3 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define IMX_SC_R_GPT_4 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define IMX_SC_R_KPP 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define IMX_SC_R_MU_0A 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define IMX_SC_R_MU_1A 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define IMX_SC_R_MU_2A 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define IMX_SC_R_MU_3A 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define IMX_SC_R_MU_4A 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define IMX_SC_R_MU_5A 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define IMX_SC_R_MU_6A 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define IMX_SC_R_MU_7A 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define IMX_SC_R_MU_8A 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define IMX_SC_R_MU_9A 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define IMX_SC_R_MU_10A 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define IMX_SC_R_MU_11A 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define IMX_SC_R_MU_12A 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define IMX_SC_R_MU_13A 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define IMX_SC_R_MU_5B 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define IMX_SC_R_MU_6B 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define IMX_SC_R_MU_7B 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define IMX_SC_R_MU_8B 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define IMX_SC_R_MU_9B 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define IMX_SC_R_MU_10B 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define IMX_SC_R_MU_11B 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define IMX_SC_R_MU_12B 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define IMX_SC_R_MU_13B 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define IMX_SC_R_ROM_0 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define IMX_SC_R_FSPI_0 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define IMX_SC_R_FSPI_1 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define IMX_SC_R_IEE 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define IMX_SC_R_IEE_R0 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define IMX_SC_R_IEE_R1 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define IMX_SC_R_IEE_R2 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define IMX_SC_R_IEE_R3 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define IMX_SC_R_IEE_R4 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define IMX_SC_R_IEE_R5 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define IMX_SC_R_IEE_R6 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define IMX_SC_R_IEE_R7 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define IMX_SC_R_SDHC_0 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define IMX_SC_R_SDHC_1 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define IMX_SC_R_SDHC_2 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define IMX_SC_R_ENET_0 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define IMX_SC_R_ENET_1 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define IMX_SC_R_MLB_0 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define IMX_SC_R_DMA_2_CH0 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define IMX_SC_R_DMA_2_CH1 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define IMX_SC_R_DMA_2_CH2 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define IMX_SC_R_DMA_2_CH3 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define IMX_SC_R_DMA_2_CH4 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define IMX_SC_R_USB_0 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define IMX_SC_R_USB_1 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define IMX_SC_R_USB_0_PHY 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define IMX_SC_R_USB_2 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define IMX_SC_R_USB_2_PHY 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define IMX_SC_R_DTCP 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define IMX_SC_R_NAND 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define IMX_SC_R_LVDS_0 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define IMX_SC_R_LVDS_0_PWM_0 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define IMX_SC_R_LVDS_0_I2C_0 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define IMX_SC_R_LVDS_0_I2C_1 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define IMX_SC_R_LVDS_1 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define IMX_SC_R_LVDS_1_PWM_0 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define IMX_SC_R_LVDS_1_I2C_0 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define IMX_SC_R_LVDS_1_I2C_1 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define IMX_SC_R_LVDS_2 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define IMX_SC_R_LVDS_2_PWM_0 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define IMX_SC_R_LVDS_2_I2C_0 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define IMX_SC_R_LVDS_2_I2C_1 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define IMX_SC_R_M4_0_PID0 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define IMX_SC_R_M4_0_PID1 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define IMX_SC_R_M4_0_PID2 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define IMX_SC_R_M4_0_PID3 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define IMX_SC_R_M4_0_PID4 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define IMX_SC_R_M4_0_RGPIO 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define IMX_SC_R_M4_0_SEMA42 284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define IMX_SC_R_M4_0_TPM 285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define IMX_SC_R_M4_0_PIT 286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define IMX_SC_R_M4_0_UART 287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define IMX_SC_R_M4_0_I2C 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define IMX_SC_R_M4_0_INTMUX 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define IMX_SC_R_M4_0_MU_0B 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define IMX_SC_R_M4_0_MU_0A0 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define IMX_SC_R_M4_0_MU_0A1 294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define IMX_SC_R_M4_0_MU_0A2 295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define IMX_SC_R_M4_0_MU_0A3 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define IMX_SC_R_M4_0_MU_1A 297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define IMX_SC_R_M4_1_PID0 298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define IMX_SC_R_M4_1_PID1 299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define IMX_SC_R_M4_1_PID2 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define IMX_SC_R_M4_1_PID3 301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define IMX_SC_R_M4_1_PID4 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define IMX_SC_R_M4_1_RGPIO 303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define IMX_SC_R_M4_1_SEMA42 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define IMX_SC_R_M4_1_TPM 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define IMX_SC_R_M4_1_PIT 306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define IMX_SC_R_M4_1_UART 307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define IMX_SC_R_M4_1_I2C 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define IMX_SC_R_M4_1_INTMUX 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define IMX_SC_R_M4_1_MU_0B 312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define IMX_SC_R_M4_1_MU_0A0 313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define IMX_SC_R_M4_1_MU_0A1 314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define IMX_SC_R_M4_1_MU_0A2 315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define IMX_SC_R_M4_1_MU_0A3 316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define IMX_SC_R_M4_1_MU_1A 317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define IMX_SC_R_SAI_0 318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define IMX_SC_R_SAI_1 319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define IMX_SC_R_SAI_2 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define IMX_SC_R_IRQSTR_SCU2 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define IMX_SC_R_IRQSTR_DSP 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define IMX_SC_R_ELCDIF_PLL 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define IMX_SC_R_OCRAM 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define IMX_SC_R_AUDIO_PLL_0 325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define IMX_SC_R_PI_0 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define IMX_SC_R_PI_0_PWM_0 327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define IMX_SC_R_PI_0_PWM_1 328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define IMX_SC_R_PI_0_I2C_0 329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define IMX_SC_R_PI_0_PLL 330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define IMX_SC_R_PI_1 331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define IMX_SC_R_PI_1_PWM_0 332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define IMX_SC_R_PI_1_PWM_1 333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define IMX_SC_R_PI_1_I2C_0 334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define IMX_SC_R_PI_1_PLL 335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define IMX_SC_R_SC_PID0 336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define IMX_SC_R_SC_PID1 337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define IMX_SC_R_SC_PID2 338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define IMX_SC_R_SC_PID3 339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define IMX_SC_R_SC_PID4 340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define IMX_SC_R_SC_SEMA42 341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define IMX_SC_R_SC_TPM 342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define IMX_SC_R_SC_PIT 343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define IMX_SC_R_SC_UART 344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define IMX_SC_R_SC_I2C 345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define IMX_SC_R_SC_MU_0B 346
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define IMX_SC_R_SC_MU_0A0 347
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define IMX_SC_R_SC_MU_0A1 348
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define IMX_SC_R_SC_MU_0A2 349
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define IMX_SC_R_SC_MU_0A3 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define IMX_SC_R_SC_MU_1A 351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define IMX_SC_R_SYSCNT_RD 352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define IMX_SC_R_SYSCNT_CMP 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define IMX_SC_R_DEBUG 354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define IMX_SC_R_SYSTEM 355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define IMX_SC_R_SNVS 356
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define IMX_SC_R_OTP 357
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define IMX_SC_R_VPU_PID0 358
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define IMX_SC_R_VPU_PID1 359
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define IMX_SC_R_VPU_PID2 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define IMX_SC_R_VPU_PID3 361
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define IMX_SC_R_VPU_PID4 362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define IMX_SC_R_VPU_PID5 363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define IMX_SC_R_VPU_PID6 364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define IMX_SC_R_VPU_PID7 365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define IMX_SC_R_VPU_UART 366
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define IMX_SC_R_VPUCORE 367
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define IMX_SC_R_VPUCORE_0 368
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define IMX_SC_R_VPUCORE_1 369
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define IMX_SC_R_VPUCORE_2 370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define IMX_SC_R_VPUCORE_3 371
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define IMX_SC_R_DMA_4_CH0 372
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define IMX_SC_R_DMA_4_CH1 373
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define IMX_SC_R_DMA_4_CH2 374
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define IMX_SC_R_DMA_4_CH3 375
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define IMX_SC_R_DMA_4_CH4 376
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define IMX_SC_R_ISI_CH0 377
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define IMX_SC_R_ISI_CH1 378
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define IMX_SC_R_ISI_CH2 379
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define IMX_SC_R_ISI_CH3 380
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define IMX_SC_R_ISI_CH4 381
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define IMX_SC_R_ISI_CH5 382
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define IMX_SC_R_ISI_CH6 383
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define IMX_SC_R_ISI_CH7 384
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define IMX_SC_R_MJPEG_DEC_S0 385
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define IMX_SC_R_MJPEG_DEC_S1 386
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define IMX_SC_R_MJPEG_DEC_S2 387
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define IMX_SC_R_MJPEG_DEC_S3 388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define IMX_SC_R_MJPEG_ENC_S0 389
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define IMX_SC_R_MJPEG_ENC_S1 390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define IMX_SC_R_MJPEG_ENC_S2 391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define IMX_SC_R_MJPEG_ENC_S3 392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define IMX_SC_R_MIPI_0 393
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define IMX_SC_R_MIPI_0_PWM_0 394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define IMX_SC_R_MIPI_0_I2C_0 395
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define IMX_SC_R_MIPI_0_I2C_1 396
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define IMX_SC_R_MIPI_1 397
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define IMX_SC_R_MIPI_1_PWM_0 398
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define IMX_SC_R_MIPI_1_I2C_0 399
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define IMX_SC_R_MIPI_1_I2C_1 400
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define IMX_SC_R_CSI_0 401
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define IMX_SC_R_CSI_0_PWM_0 402
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define IMX_SC_R_CSI_0_I2C_0 403
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define IMX_SC_R_CSI_1 404
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define IMX_SC_R_CSI_1_PWM_0 405
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define IMX_SC_R_CSI_1_I2C_0 406
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define IMX_SC_R_HDMI 407
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define IMX_SC_R_HDMI_I2S 408
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define IMX_SC_R_HDMI_I2C_0 409
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define IMX_SC_R_HDMI_PLL_0 410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define IMX_SC_R_HDMI_RX 411
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define IMX_SC_R_HDMI_RX_BYPASS 412
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define IMX_SC_R_HDMI_RX_I2C_0 413
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define IMX_SC_R_ASRC_0 414
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define IMX_SC_R_ESAI_0 415
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define IMX_SC_R_SPDIF_0 416
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define IMX_SC_R_SPDIF_1 417
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define IMX_SC_R_SAI_3 418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define IMX_SC_R_SAI_4 419
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define IMX_SC_R_SAI_5 420
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #define IMX_SC_R_GPT_5 421
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define IMX_SC_R_GPT_6 422
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define IMX_SC_R_GPT_7 423
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define IMX_SC_R_GPT_8 424
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define IMX_SC_R_GPT_9 425
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define IMX_SC_R_GPT_10 426
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define IMX_SC_R_DMA_2_CH5 427
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define IMX_SC_R_DMA_2_CH6 428
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define IMX_SC_R_DMA_2_CH7 429
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define IMX_SC_R_DMA_2_CH8 430
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define IMX_SC_R_DMA_2_CH9 431
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define IMX_SC_R_DMA_2_CH10 432
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define IMX_SC_R_DMA_2_CH11 433
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define IMX_SC_R_DMA_2_CH12 434
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define IMX_SC_R_DMA_2_CH13 435
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define IMX_SC_R_DMA_2_CH14 436
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) #define IMX_SC_R_DMA_2_CH15 437
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define IMX_SC_R_DMA_2_CH16 438
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define IMX_SC_R_DMA_2_CH17 439
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define IMX_SC_R_DMA_2_CH18 440
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define IMX_SC_R_DMA_2_CH19 441
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define IMX_SC_R_DMA_2_CH20 442
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define IMX_SC_R_DMA_2_CH21 443
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define IMX_SC_R_DMA_2_CH22 444
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define IMX_SC_R_DMA_2_CH23 445
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define IMX_SC_R_DMA_2_CH24 446
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define IMX_SC_R_DMA_2_CH25 447
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define IMX_SC_R_DMA_2_CH26 448
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define IMX_SC_R_DMA_2_CH27 449
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define IMX_SC_R_DMA_2_CH28 450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define IMX_SC_R_DMA_2_CH29 451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define IMX_SC_R_DMA_2_CH30 452
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define IMX_SC_R_DMA_2_CH31 453
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define IMX_SC_R_ASRC_1 454
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) #define IMX_SC_R_ESAI_1 455
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define IMX_SC_R_SAI_6 456
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define IMX_SC_R_SAI_7 457
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define IMX_SC_R_AMIX 458
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define IMX_SC_R_MQS_0 459
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define IMX_SC_R_DMA_3_CH0 460
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define IMX_SC_R_DMA_3_CH1 461
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define IMX_SC_R_DMA_3_CH2 462
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define IMX_SC_R_DMA_3_CH3 463
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define IMX_SC_R_DMA_3_CH4 464
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define IMX_SC_R_DMA_3_CH5 465
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define IMX_SC_R_DMA_3_CH6 466
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define IMX_SC_R_DMA_3_CH7 467
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define IMX_SC_R_DMA_3_CH8 468
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define IMX_SC_R_DMA_3_CH9 469
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define IMX_SC_R_DMA_3_CH10 470
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) #define IMX_SC_R_DMA_3_CH11 471
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define IMX_SC_R_DMA_3_CH12 472
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define IMX_SC_R_DMA_3_CH13 473
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define IMX_SC_R_DMA_3_CH14 474
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define IMX_SC_R_DMA_3_CH15 475
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define IMX_SC_R_DMA_3_CH16 476
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define IMX_SC_R_DMA_3_CH17 477
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define IMX_SC_R_DMA_3_CH18 478
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define IMX_SC_R_DMA_3_CH19 479
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define IMX_SC_R_DMA_3_CH20 480
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define IMX_SC_R_DMA_3_CH21 481
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define IMX_SC_R_DMA_3_CH22 482
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define IMX_SC_R_DMA_3_CH23 483
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define IMX_SC_R_DMA_3_CH24 484
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) #define IMX_SC_R_DMA_3_CH25 485
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define IMX_SC_R_DMA_3_CH26 486
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define IMX_SC_R_DMA_3_CH27 487
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define IMX_SC_R_DMA_3_CH28 488
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define IMX_SC_R_DMA_3_CH29 489
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define IMX_SC_R_DMA_3_CH30 490
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define IMX_SC_R_DMA_3_CH31 491
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define IMX_SC_R_AUDIO_PLL_1 492
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define IMX_SC_R_AUDIO_CLK_0 493
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define IMX_SC_R_AUDIO_CLK_1 494
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define IMX_SC_R_MCLK_OUT_0 495
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define IMX_SC_R_MCLK_OUT_1 496
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define IMX_SC_R_PMIC_0 497
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define IMX_SC_R_PMIC_1 498
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define IMX_SC_R_SECO 499
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define IMX_SC_R_CAAM_JR1 500
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define IMX_SC_R_CAAM_JR2 501
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define IMX_SC_R_CAAM_JR3 502
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) #define IMX_SC_R_SECO_MU_2 503
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define IMX_SC_R_SECO_MU_3 504
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define IMX_SC_R_SECO_MU_4 505
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define IMX_SC_R_HDMI_RX_PWM_0 506
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define IMX_SC_R_A35 507
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define IMX_SC_R_A35_0 508
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define IMX_SC_R_A35_1 509
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define IMX_SC_R_A35_2 510
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define IMX_SC_R_A35_3 511
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define IMX_SC_R_DSP 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define IMX_SC_R_DSP_RAM 513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define IMX_SC_R_CAAM_JR1_OUT 514
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define IMX_SC_R_CAAM_JR2_OUT 515
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define IMX_SC_R_CAAM_JR3_OUT 516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define IMX_SC_R_VPU_DEC_0 517
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define IMX_SC_R_VPU_ENC_0 518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define IMX_SC_R_CAAM_JR0 519
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define IMX_SC_R_CAAM_JR0_OUT 520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) #define IMX_SC_R_PMIC_2 521
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define IMX_SC_R_DBLOGIC 522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define IMX_SC_R_HDMI_PLL_1 523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define IMX_SC_R_BOARD_R0 524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define IMX_SC_R_BOARD_R1 525
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define IMX_SC_R_BOARD_R2 526
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define IMX_SC_R_BOARD_R3 527
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define IMX_SC_R_BOARD_R4 528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define IMX_SC_R_BOARD_R5 529
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define IMX_SC_R_BOARD_R6 530
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define IMX_SC_R_BOARD_R7 531
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define IMX_SC_R_MJPEG_DEC_MP 532
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define IMX_SC_R_MJPEG_ENC_MP 533
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define IMX_SC_R_VPU_TS_0 534
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define IMX_SC_R_VPU_MU_0 535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define IMX_SC_R_VPU_MU_1 536
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) #define IMX_SC_R_VPU_MU_2 537
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define IMX_SC_R_VPU_MU_3 538
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define IMX_SC_R_VPU_ENC_1 539
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define IMX_SC_R_VPU 540
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define IMX_SC_R_DMA_5_CH0 541
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define IMX_SC_R_DMA_5_CH1 542
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define IMX_SC_R_DMA_5_CH2 543
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define IMX_SC_R_DMA_5_CH3 544
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define IMX_SC_R_ATTESTATION 545
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define IMX_SC_R_LAST 546
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) * Defines for SC PM CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define IMX_SC_PM_CLK_SLV_BUS 0 /* Slave bus clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define IMX_SC_PM_CLK_MST_BUS 1 /* Master bus clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define IMX_SC_PM_CLK_PER 2 /* Peripheral clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define IMX_SC_PM_CLK_PHY 3 /* Phy clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) #define IMX_SC_PM_CLK_MISC 4 /* Misc clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define IMX_SC_PM_CLK_MISC0 0 /* Misc 0 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define IMX_SC_PM_CLK_MISC1 1 /* Misc 1 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define IMX_SC_PM_CLK_MISC2 2 /* Misc 2 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define IMX_SC_PM_CLK_MISC3 3 /* Misc 3 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define IMX_SC_PM_CLK_MISC4 4 /* Misc 4 clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define IMX_SC_PM_CLK_CPU 2 /* CPU clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define IMX_SC_PM_CLK_PLL 4 /* PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define IMX_SC_PM_CLK_BYPASS 4 /* Bypass clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) * Defines for SC CONTROL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define IMX_SC_C_TEMP 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define IMX_SC_C_TEMP_HI 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define IMX_SC_C_TEMP_LOW 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) #define IMX_SC_C_PXL_LINK_MST1_ADDR 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define IMX_SC_C_PXL_LINK_MST2_ADDR 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define IMX_SC_C_PXL_LINK_MST_ENB 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define IMX_SC_C_PXL_LINK_MST1_ENB 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define IMX_SC_C_PXL_LINK_MST2_ENB 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define IMX_SC_C_PXL_LINK_SLV1_ADDR 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define IMX_SC_C_PXL_LINK_SLV2_ADDR 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define IMX_SC_C_PXL_LINK_MST_VLD 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define IMX_SC_C_PXL_LINK_MST1_VLD 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define IMX_SC_C_PXL_LINK_MST2_VLD 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define IMX_SC_C_SINGLE_MODE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define IMX_SC_C_ID 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define IMX_SC_C_PXL_CLK_POLARITY 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define IMX_SC_C_LINESTATE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) #define IMX_SC_C_PCIE_G_RST 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define IMX_SC_C_PCIE_BUTTON_RST 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define IMX_SC_C_PCIE_PERST 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define IMX_SC_C_PHY_RESET 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define IMX_SC_C_PXL_LINK_RATE_CORRECTION 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define IMX_SC_C_PANIC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define IMX_SC_C_PRIORITY_GROUP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define IMX_SC_C_TXCLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define IMX_SC_C_CLKDIV 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define IMX_SC_C_DISABLE_50 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define IMX_SC_C_DISABLE_125 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define IMX_SC_C_SEL_125 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define IMX_SC_C_MODE 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define IMX_SC_C_SYNC_CTRL0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) #define IMX_SC_C_KACHUNK_CNT 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define IMX_SC_C_KACHUNK_SEL 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define IMX_SC_C_SYNC_CTRL1 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define IMX_SC_C_DPI_RESET 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define IMX_SC_C_MIPI_RESET 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define IMX_SC_C_DUAL_MODE 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define IMX_SC_C_VOLTAGE 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define IMX_SC_C_PXL_LINK_SEL 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define IMX_SC_C_OFS_SEL 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define IMX_SC_C_OFS_AUDIO 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define IMX_SC_C_OFS_PERIPH 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define IMX_SC_C_OFS_IRQ 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define IMX_SC_C_RST0 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define IMX_SC_C_RST1 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define IMX_SC_C_SEL0 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define IMX_SC_C_CALIB0 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define IMX_SC_C_CALIB1 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define IMX_SC_C_CALIB2 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) #define IMX_SC_C_IPG_DEBUG 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define IMX_SC_C_IPG_DOZE 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define IMX_SC_C_IPG_WAIT 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define IMX_SC_C_IPG_STOP 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define IMX_SC_C_IPG_STOP_MODE 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define IMX_SC_C_IPG_STOP_ACK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define IMX_SC_C_SYNC_CTRL 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define IMX_SC_C_OFS_AUDIO_ALT 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define IMX_SC_C_DSP_BYP 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define IMX_SC_C_CLK_GEN_EN 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define IMX_SC_C_INTF_SEL 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define IMX_SC_C_RXC_DLY 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define IMX_SC_C_TIMER_SEL 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define IMX_SC_C_LAST 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #endif /* __DT_BINDINGS_RSCRC_IMX_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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