Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (C) 2011-2014 ROCKCHIP, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * This software is licensed under the terms of the GNU General Public
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * License version 2, as published by the Free Software Foundation, and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  * may be copied, distributed, and modified under those terms.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  * This program is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define _DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DDR3_DS_34ohm		(1<<1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DDR3_DS_40ohm		(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LP2_DS_34ohm		(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LP2_DS_40ohm		(0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LP2_DS_48ohm		(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LP2_DS_60ohm		(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LP2_DS_68_6ohm		(0x5)/*optional*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LP2_DS_80ohm		(0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LP2_DS_120ohm		(0x7)/*optional*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define LP3_DS_34ohm		(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LP3_DS_40ohm		(0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LP3_DS_48ohm		(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LP3_DS_60ohm		(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LP3_DS_80ohm		(0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LP3_DS_34D_40U		(0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LP3_DS_40D_48U		(0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LP3_DS_34D_48U		(0xb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DDR3_ODT_DIS		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DDR3_ODT_40ohm		((1<<2)|(1<<6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DDR3_ODT_60ohm		(1<<2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DDR3_ODT_120ohm		(1<<6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define LP3_ODT_DIS		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define LP3_ODT_60ohm		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define LP3_ODT_120ohm		(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define LP3_ODT_240ohm		(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PHY_RON_DISABLE		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PHY_RON_272ohm		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PHY_RON_135ohm		(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PHY_RON_91ohm		(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PHY_RON_38ohm		(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PHY_RON_68ohm		(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PHY_RON_54ohm		(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PHY_RON_45ohm		(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PHY_RON_39ohm		(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PHY_RON_34ohm		(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PHY_RON_30ohm		(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PHY_RON_27ohm		(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PHY_RON_25ohm		(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PHY_RTT_DISABLE		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PHY_RTT_1116ohm		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PHY_RTT_558ohm		(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PHY_RTT_372ohm		(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PHY_RTT_279ohm		(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PHY_RTT_223ohm		(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PHY_RTT_186ohm		(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PHY_RTT_159ohm		(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PHY_RTT_139ohm		(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PHY_RTT_124ohm		(9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PHY_RTT_112ohm		(10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PHY_RTT_101ohm		(11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PHY_RTT_93ohm		(12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PHY_RTT_86ohm		(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PHY_RTT_80ohm		(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PHY_RTT_74ohm		(15)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #endif /*_DT_BINDINGS_DRAM_ROCKCHIP_RK3368_H*/