Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * Copyright (c) 2018 Fuzhou Rockchip Electronics Co., Ltd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * SPDX-License-Identifier: GPL-2.0+
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define DDR3_DS_34ohm		(1 << 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define DDR3_DS_40ohm		(0x0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LP2_DS_34ohm		(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define LP2_DS_40ohm		(0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define LP2_DS_48ohm		(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define LP2_DS_60ohm		(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define LP2_DS_68_6ohm		(0x5)/* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define LP2_DS_80ohm		(0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define LP2_DS_120ohm		(0x7)/* optional */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define LP3_DS_34ohm		(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define LP3_DS_40ohm		(0x2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LP3_DS_48ohm		(0x3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define LP3_DS_60ohm		(0x4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LP3_DS_80ohm		(0x6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define LP3_DS_34D_40U		(0x9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define LP3_DS_40D_48U		(0xa)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define LP3_DS_34D_48U		(0xb)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DDR3_ODT_DIS		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DDR3_ODT_40ohm		((1 << 2) | (1 << 6))
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DDR3_ODT_60ohm		(1 << 2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DDR3_ODT_120ohm		(1 << 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LP3_ODT_DIS		(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LP3_ODT_60ohm		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LP3_ODT_120ohm		(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LP3_ODT_240ohm		(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PHY_DDR3_RON_RTT_DISABLE	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PHY_DDR3_RON_RTT_451ohm		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PHY_DDR3_RON_RTT_225ohm		(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PHY_DDR3_RON_RTT_150ohm		(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PHY_DDR3_RON_RTT_112ohm		(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PHY_DDR3_RON_RTT_90ohm		(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PHY_DDR3_RON_RTT_75ohm		(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PHY_DDR3_RON_RTT_64ohm		(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PHY_DDR3_RON_RTT_56ohm		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PHY_DDR3_RON_RTT_50ohm		(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PHY_DDR3_RON_RTT_45ohm		(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PHY_DDR3_RON_RTT_41ohm		(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PHY_DDR3_RON_RTT_37ohm		(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PHY_DDR3_RON_RTT_34ohm		(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PHY_DDR3_RON_RTT_33ohm		(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PHY_DDR3_RON_RTT_30ohm		(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PHY_DDR3_RON_RTT_28ohm		(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PHY_DDR3_RON_RTT_26ohm		(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PHY_DDR3_RON_RTT_25ohm		(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PHY_DDR3_RON_RTT_23ohm		(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define PHY_DDR3_RON_RTT_22ohm		(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define PHY_DDR3_RON_RTT_21ohm		(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define PHY_DDR3_RON_RTT_20ohm		(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PHY_DDR3_RON_RTT_19ohm		(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PHY_LP23_RON_RTT_DISABLE	(0)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PHY_LP23_RON_RTT_480ohm		(1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PHY_LP23_RON_RTT_240ohm		(2)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PHY_LP23_RON_RTT_160ohm		(3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PHY_LP23_RON_RTT_120ohm		(4)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PHY_LP23_RON_RTT_96ohm		(5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PHY_LP23_RON_RTT_80ohm		(6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PHY_LP23_RON_RTT_68ohm		(7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PHY_LP23_RON_RTT_60ohm		(16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PHY_LP23_RON_RTT_53ohm		(17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PHY_LP23_RON_RTT_48ohm		(18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PHY_LP23_RON_RTT_43ohm		(19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PHY_LP23_RON_RTT_40ohm		(20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PHY_LP23_RON_RTT_37ohm		(21)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PHY_LP23_RON_RTT_34ohm		(22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PHY_LP23_RON_RTT_32ohm		(23)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PHY_LP23_RON_RTT_30ohm		(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PHY_LP23_RON_RTT_28ohm		(25)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PHY_LP23_RON_RTT_26ohm		(26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PHY_LP23_RON_RTT_25ohm		(27)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PHY_LP23_RON_RTT_24ohm		(28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PHY_LP23_RON_RTT_22ohm		(29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PHY_LP23_RON_RTT_21ohm		(30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PHY_LP23_RON_RTT_20ohm		(31)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #endif /* _DT_BINDINGS_DRAM_ROCKCHIP_RK322X_H */