Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides macros for X1830 DMA bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (c) 2019 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __DT_BINDINGS_DMA_X1830_DMA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __DT_BINDINGS_DMA_X1830_DMA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * Request type numbers for the X1830 DMA controller (written to the DRTn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * register for the channel).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define X1830_DMA_I2S0_TX	0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define X1830_DMA_I2S0_RX	0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define X1830_DMA_AUTO		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define X1830_DMA_SADC_RX	0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define X1830_DMA_UART1_TX	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define X1830_DMA_UART1_RX	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define X1830_DMA_UART0_TX	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define X1830_DMA_UART0_RX	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define X1830_DMA_SSI0_TX	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define X1830_DMA_SSI0_RX	0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define X1830_DMA_SSI1_TX	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define X1830_DMA_SSI1_RX	0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define X1830_DMA_MSC0_TX	0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define X1830_DMA_MSC0_RX	0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define X1830_DMA_MSC1_TX	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define X1830_DMA_MSC1_RX	0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define X1830_DMA_DMIC_RX	0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define X1830_DMA_SMB0_TX	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define X1830_DMA_SMB0_RX	0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define X1830_DMA_SMB1_TX	0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define X1830_DMA_SMB1_RX	0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define X1830_DMA_DES_TX	0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define X1830_DMA_DES_RX	0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #endif /* __DT_BINDINGS_DMA_X1830_DMA_H__ */