Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) #ifndef __DT_BINDINGS_DMA_JZ4780_DMA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) #define __DT_BINDINGS_DMA_JZ4780_DMA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Request type numbers for the JZ4780 DMA controller (written to the DRTn
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * register for the channel).
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define JZ4780_DMA_I2S1_TX	0x4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define JZ4780_DMA_I2S1_RX	0x5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define JZ4780_DMA_I2S0_TX	0x6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define JZ4780_DMA_I2S0_RX	0x7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define JZ4780_DMA_AUTO		0x8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define JZ4780_DMA_SADC_RX	0x9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define JZ4780_DMA_UART4_TX	0xc
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define JZ4780_DMA_UART4_RX	0xd
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define JZ4780_DMA_UART3_TX	0xe
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define JZ4780_DMA_UART3_RX	0xf
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define JZ4780_DMA_UART2_TX	0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define JZ4780_DMA_UART2_RX	0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define JZ4780_DMA_UART1_TX	0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define JZ4780_DMA_UART1_RX	0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define JZ4780_DMA_UART0_TX	0x14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define JZ4780_DMA_UART0_RX	0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define JZ4780_DMA_SSI0_TX	0x16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define JZ4780_DMA_SSI0_RX	0x17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define JZ4780_DMA_SSI1_TX	0x18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define JZ4780_DMA_SSI1_RX	0x19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define JZ4780_DMA_MSC0_TX	0x1a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define JZ4780_DMA_MSC0_RX	0x1b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define JZ4780_DMA_MSC1_TX	0x1c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define JZ4780_DMA_MSC1_RX	0x1d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define JZ4780_DMA_MSC2_TX	0x1e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define JZ4780_DMA_MSC2_RX	0x1f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define JZ4780_DMA_PCM0_TX	0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define JZ4780_DMA_PCM0_RX	0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define JZ4780_DMA_SMB0_TX	0x24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define JZ4780_DMA_SMB0_RX	0x25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define JZ4780_DMA_SMB1_TX	0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define JZ4780_DMA_SMB1_RX	0x27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define JZ4780_DMA_SMB2_TX	0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define JZ4780_DMA_SMB2_RX	0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define JZ4780_DMA_SMB3_TX	0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define JZ4780_DMA_SMB3_RX	0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define JZ4780_DMA_SMB4_TX	0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define JZ4780_DMA_SMB4_RX	0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define JZ4780_DMA_DES_TX	0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define JZ4780_DMA_DES_RX	0x2f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #endif /* __DT_BINDINGS_DMA_JZ4780_DMA_H__ */