Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides macros for at91 dma bindings.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2013 Ludovic Desroches <ludovic.desroches@atmel.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef __DT_BINDINGS_AT91_DMA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define __DT_BINDINGS_AT91_DMA_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* ---------- HDMAC ---------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * Source and/or destination peripheral ID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define AT91_DMA_CFG_PER_ID_MASK	(0xff)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define AT91_DMA_CFG_PER_ID(id)		(id & AT91_DMA_CFG_PER_ID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)  * FIFO configuration: it defines when a request is serviced.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define AT91_DMA_CFG_FIFOCFG_OFFSET	(8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define AT91_DMA_CFG_FIFOCFG_MASK	(0xf << AT91_DMA_CFG_FIFOCFG_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define AT91_DMA_CFG_FIFOCFG_HALF	(0x0 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* half FIFO (default behavior) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define AT91_DMA_CFG_FIFOCFG_ALAP	(0x1 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* largest defined AHB burst */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define AT91_DMA_CFG_FIFOCFG_ASAP	(0x2 << AT91_DMA_CFG_FIFOCFG_OFFSET)	/* single AHB access */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* ---------- XDMAC ---------- */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define AT91_XDMAC_DT_MEM_IF_MASK	(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define AT91_XDMAC_DT_MEM_IF_OFFSET	(13)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define AT91_XDMAC_DT_MEM_IF(mem_if)	(((mem_if) & AT91_XDMAC_DT_MEM_IF_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) 					<< AT91_XDMAC_DT_MEM_IF_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define AT91_XDMAC_DT_GET_MEM_IF(cfg)	(((cfg) >> AT91_XDMAC_DT_MEM_IF_OFFSET) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) 					& AT91_XDMAC_DT_MEM_IF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define AT91_XDMAC_DT_PER_IF_MASK	(0x1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define AT91_XDMAC_DT_PER_IF_OFFSET	(14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define AT91_XDMAC_DT_PER_IF(per_if)	(((per_if) & AT91_XDMAC_DT_PER_IF_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 					<< AT91_XDMAC_DT_PER_IF_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define AT91_XDMAC_DT_GET_PER_IF(cfg)	(((cfg) >> AT91_XDMAC_DT_PER_IF_OFFSET) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) 					& AT91_XDMAC_DT_PER_IF_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AT91_XDMAC_DT_PERID_MASK	(0x7f)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AT91_XDMAC_DT_PERID_OFFSET	(24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AT91_XDMAC_DT_PERID(perid)	(((perid) & AT91_XDMAC_DT_PERID_MASK) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) 					<< AT91_XDMAC_DT_PERID_OFFSET)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define AT91_XDMAC_DT_GET_PERID(cfg)	(((cfg) >> AT91_XDMAC_DT_PERID_OFFSET) \
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) 					& AT91_XDMAC_DT_PERID_MASK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #endif /* __DT_BINDINGS_AT91_DMA_H__ */