^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) drivers/video/rockchip/transmitter/mipi_dsi.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef MIPI_DSI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define MIPI_DSI_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifdef CONFIG_MIPI_DSI_FT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #include "..\..\common\config.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) //DSI DATA TYPE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define DTYPE_DCS_SWRITE_0P 0x05
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define DTYPE_DCS_SWRITE_1P 0x15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DTYPE_DCS_LWRITE 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define DTYPE_GEN_LWRITE 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define DTYPE_GEN_SWRITE_2P 0x23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define DTYPE_GEN_SWRITE_1P 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define DTYPE_GEN_SWRITE_0P 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) //command transmit mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define HSDT 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define LPDT 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) //DSI DATA TYPE FLAG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DATA_TYPE_DCS 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DATA_TYPE_GEN 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) //Video Mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define VM_NBMWSP 0x00 //Non burst mode with sync pulses
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define VM_NBMWSE 0x01 //Non burst mode with sync events
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define VM_BM 0x02 //Burst mode
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) //Video Pixel Format
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define VPF_16BPP 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define VPF_18BPP 0x01 //packed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define VPF_18BPPL 0x02 //loosely packed
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define VPF_24BPP 0x03
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) //Display Command Set
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define dcs_enter_idle_mode 0x39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define dcs_enter_invert_mode 0x21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define dcs_enter_normal_mode 0x13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define dcs_enter_partial_mode 0x12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define dcs_enter_sleep_mode 0x10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define dcs_exit_idle_mode 0x38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define dcs_exit_invert_mode 0x20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define dcs_exit_sleep_mode 0x11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define dcs_get_address_mode 0x0b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define dcs_get_blue_channel 0x08
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define dcs_get_diagnostic_result 0x0f
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define dcs_get_display_mode 0x0d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define dcs_get_green_channel 0x07
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define dcs_get_pixel_format 0x0c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define dcs_get_power_mode 0x0a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define dcs_get_red_channel 0x06
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define dcs_get_scanline 0x45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define dcs_get_signal_mode 0x0e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define dcs_nop 0x00
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define dcs_read_DDB_continue 0xa8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define dcs_read_DDB_start 0xa1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define dcs_read_memory_continue 0x3e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define dcs_read_memory_start 0x2e
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define dcs_set_address_mode 0x36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define dcs_set_column_address 0x2a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define dcs_set_display_off 0x28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define dcs_set_display_on 0x29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define dcs_set_gamma_curve 0x26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define dcs_set_page_address 0x2b
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define dcs_set_partial_area 0x30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define dcs_set_pixel_format 0x3a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define dcs_set_scroll_area 0x33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define dcs_set_scroll_start 0x37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define dcs_set_tear_off 0x34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define dcs_set_tear_on 0x35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define dcs_set_tear_scanline 0x44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define dcs_soft_reset 0x01
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define dcs_write_LUT 0x2d
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define dcs_write_memory_continue 0x3c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define dcs_write_memory_start 0x2c
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #ifndef MHz
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define MHz 1000000
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #if 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) typedef signed char s8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) typedef unsigned char u8;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) typedef signed short s16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) typedef unsigned short u16;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) typedef signed int s32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) typedef unsigned int u32;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) typedef signed long s64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) typedef unsigned long u64;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #endif
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) //iomux
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OLD_RK_IOMUX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #endif /* end of MIPI_DSI_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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