^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2015 - 2016 ZTE Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #ifndef __DT_BINDINGS_CLOCK_ZX296718_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define __DT_BINDINGS_CLOCK_ZX296718_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) /* PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define ZX296718_PLL_CPU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ZX296718_PLL_MAC 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ZX296718_PLL_MM0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ZX296718_PLL_MM1 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ZX296718_PLL_VGA 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ZX296718_PLL_DDR 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ZX296718_PLL_AUDIO 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ZX296718_PLL_HSIC 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CPU_DBG_GATE 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define A72_GATE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CPU_PERI_GATE 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define A53_GATE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define DDR1_GATE 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define DDR0_GATE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SD1_WCLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SD1_AHB 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SD0_WCLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define SD0_AHB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EMMC_WCLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define EMMC_NAND_AXI 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define NAND_WCLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define EMMC_NAND_AHB 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define LSP1_148M5 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define LSP1_99M 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define LSP1_24M 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define LSP0_74M25 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define LSP0_32K 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define LSP0_148M5 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define LSP0_99M 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define LSP0_24M 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define DEMUX_AXI 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define DEMUX_APB 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define DEMUX_148M5 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define DEMUX_108M 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define AUDIO_APB 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define AUDIO_99M 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define AUDIO_24M 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define AUDIO_16M384 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define AUDIO_32K 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define WDT_WCLK 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TIMER_WCLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define VDE_ACLK 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define VCE_ACLK 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HDE_ACLK 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define GPU_ACLK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SAPPU_ACLK 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define SAPPU_WCLK 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define VOU_ACLK 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define VOU_MAIN_WCLK 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define VOU_AUX_WCLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define VOU_PPU_WCLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MIPI_CFG_CLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define VGA_I2C_WCLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define MIPI_REF_CLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HDMI_OSC_CEC 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HDMI_OSC_CLK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HDMI_XCLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define VIU_M0_ACLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define VIU_M1_ACLK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define VIU_WCLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define VIU_JPEG_WCLK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define VIU_CFG_CLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TS_SYS_WCLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TS_SYS_108M 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define USB20_HCLK 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define USB20_PHY_CLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define USB21_HCLK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define USB21_PHY_CLK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define GMAC_RMIICLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define GMAC_PCLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GMAC_ACLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GMAC_RFCLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TEMPSENSOR_GATE 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TOP_NR_CLKS 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define LSP0_TIMER3_PCLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define LSP0_TIMER3_WCLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define LSP0_TIMER4_PCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define LSP0_TIMER4_WCLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define LSP0_TIMER5_PCLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define LSP0_TIMER5_WCLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define LSP0_UART3_PCLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define LSP0_UART3_WCLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define LSP0_UART1_PCLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define LSP0_UART1_WCLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define LSP0_UART2_PCLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define LSP0_UART2_WCLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define LSP0_SPIFC0_PCLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define LSP0_SPIFC0_WCLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define LSP0_I2C4_PCLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define LSP0_I2C4_WCLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define LSP0_I2C5_PCLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define LSP0_I2C5_WCLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define LSP0_SSP0_PCLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define LSP0_SSP0_WCLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define LSP0_SSP1_PCLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define LSP0_SSP1_WCLK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define LSP0_USIM_PCLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define LSP0_USIM_WCLK 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define LSP0_GPIO_PCLK 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define LSP0_GPIO_WCLK 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define LSP0_I2C3_PCLK 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define LSP0_I2C3_WCLK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define LSP0_NR_CLKS 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define LSP1_UART4_PCLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define LSP1_UART4_WCLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define LSP1_UART5_PCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define LSP1_UART5_WCLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define LSP1_PWM_PCLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define LSP1_PWM_WCLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LSP1_I2C2_PCLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define LSP1_I2C2_WCLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define LSP1_SSP2_PCLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define LSP1_SSP2_WCLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LSP1_SSP3_PCLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define LSP1_SSP3_WCLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define LSP1_SSP4_PCLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define LSP1_SSP4_WCLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define LSP1_USIM1_PCLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define LSP1_USIM1_WCLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define LSP1_NR_CLKS 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define AUDIO_I2S0_WCLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define AUDIO_I2S0_PCLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define AUDIO_I2S1_WCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define AUDIO_I2S1_PCLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define AUDIO_I2S2_WCLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define AUDIO_I2S2_PCLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define AUDIO_I2S3_WCLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define AUDIO_I2S3_PCLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define AUDIO_I2C0_WCLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define AUDIO_I2C0_PCLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define AUDIO_SPDIF0_WCLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define AUDIO_SPDIF0_PCLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define AUDIO_SPDIF1_WCLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define AUDIO_SPDIF1_PCLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define AUDIO_TIMER_WCLK 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define AUDIO_TIMER_PCLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define AUDIO_TDM_WCLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define AUDIO_TDM_PCLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define AUDIO_TS_PCLK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define I2S0_WCLK_MUX 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define I2S1_WCLK_MUX 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define I2S2_WCLK_MUX 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define I2S3_WCLK_MUX 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define AUDIO_NR_CLKS 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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