^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2014 Linaro Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Copyright (C) 2014 ZTE Corporation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef __DT_BINDINGS_CLOCK_ZX296702_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define __DT_BINDINGS_CLOCK_ZX296702_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define ZX296702_OSC 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define ZX296702_PLL_A9 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define ZX296702_PLL_A9_350M 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define ZX296702_PLL_MAC_1000M 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define ZX296702_PLL_MAC_333M 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define ZX296702_PLL_MM0_1188M 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define ZX296702_PLL_MM0_396M 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define ZX296702_PLL_MM0_198M 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define ZX296702_PLL_MM1_108M 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define ZX296702_PLL_MM1_72M 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define ZX296702_PLL_MM1_54M 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ZX296702_PLL_LSP_104M 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ZX296702_PLL_LSP_26M 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ZX296702_PLL_AUDIO_294M912 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define ZX296702_PLL_DDR_266M 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ZX296702_CLK_148M5 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define ZX296702_MATRIX_ACLK 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define ZX296702_MAIN_HCLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define ZX296702_MAIN_PCLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ZX296702_CLK_500 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ZX296702_CLK_250 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define ZX296702_CLK_125 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define ZX296702_CLK_74M25 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define ZX296702_A9_WCLK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define ZX296702_A9_AS1_ACLK_MUX 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ZX296702_A9_TRACE_CLKIN_MUX 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define ZX296702_A9_AS1_ACLK_DIV 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define ZX296702_CLK_2 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define ZX296702_CLK_27 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define ZX296702_DECPPU_ACLK_MUX 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define ZX296702_PPU_ACLK_MUX 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define ZX296702_MALI400_ACLK_MUX 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define ZX296702_VOU_ACLK_MUX 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define ZX296702_VOU_MAIN_WCLK_MUX 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define ZX296702_VOU_AUX_WCLK_MUX 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define ZX296702_VOU_SCALER_WCLK_MUX 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define ZX296702_R2D_ACLK_MUX 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define ZX296702_R2D_WCLK_MUX 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define ZX296702_CLK_50 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define ZX296702_CLK_25 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define ZX296702_CLK_12 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define ZX296702_CLK_16M384 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define ZX296702_CLK_32K768 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define ZX296702_SEC_WCLK_DIV 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ZX296702_DDR_WCLK_MUX 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define ZX296702_NAND_WCLK_MUX 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define ZX296702_LSP_26_WCLK_MUX 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define ZX296702_A9_AS0_ACLK 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define ZX296702_A9_AS1_ACLK 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define ZX296702_A9_TRACE_CLKIN 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define ZX296702_DECPPU_AXI_M_ACLK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define ZX296702_DECPPU_AHB_S_HCLK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define ZX296702_PPU_AXI_M_ACLK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ZX296702_PPU_AHB_S_HCLK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ZX296702_VOU_AXI_M_ACLK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ZX296702_VOU_APB_PCLK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ZX296702_VOU_MAIN_CHANNEL_WCLK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define ZX296702_VOU_AUX_CHANNEL_WCLK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define ZX296702_VOU_HDMI_OSCLK_CEC 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define ZX296702_VOU_SCALER_WCLK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define ZX296702_MALI400_AXI_M_ACLK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define ZX296702_MALI400_APB_PCLK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ZX296702_R2D_WCLK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define ZX296702_R2D_AXI_M_ACLK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define ZX296702_R2D_AHB_HCLK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define ZX296702_DDR3_AXI_S0_ACLK 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define ZX296702_DDR3_APB_PCLK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define ZX296702_DDR3_WCLK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define ZX296702_USB20_0_AHB_HCLK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define ZX296702_USB20_0_EXTREFCLK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ZX296702_USB20_1_AHB_HCLK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define ZX296702_USB20_1_EXTREFCLK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define ZX296702_USB20_2_AHB_HCLK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define ZX296702_USB20_2_EXTREFCLK 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define ZX296702_GMAC_AXI_M_ACLK 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define ZX296702_GMAC_APB_PCLK 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define ZX296702_GMAC_125_CLKIN 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define ZX296702_GMAC_RMII_CLKIN 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define ZX296702_GMAC_25M_CLK 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define ZX296702_NANDFLASH_AHB_HCLK 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define ZX296702_NANDFLASH_WCLK 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define ZX296702_LSP0_APB_PCLK 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define ZX296702_LSP0_AHB_HCLK 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define ZX296702_LSP0_26M_WCLK 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define ZX296702_LSP0_104M_WCLK 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define ZX296702_LSP0_16M384_WCLK 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define ZX296702_LSP1_APB_PCLK 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define ZX296702_LSP1_26M_WCLK 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define ZX296702_LSP1_104M_WCLK 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define ZX296702_LSP1_32K_CLK 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ZX296702_AON_HCLK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ZX296702_SYS_CTRL_PCLK 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ZX296702_DMA_PCLK 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ZX296702_DMA_ACLK 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ZX296702_SEC_HCLK 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define ZX296702_AES_WCLK 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define ZX296702_DES_WCLK 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define ZX296702_IRAM_ACLK 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define ZX296702_IROM_ACLK 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define ZX296702_BOOT_CTRL_HCLK 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define ZX296702_EFUSE_CLK_30 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define ZX296702_VOU_MAIN_CHANNEL_DIV 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define ZX296702_VOU_AUX_CHANNEL_DIV 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define ZX296702_VOU_TV_ENC_HD_DIV 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define ZX296702_VOU_TV_ENC_SD_DIV 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ZX296702_VL0_MUX 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ZX296702_VL1_MUX 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ZX296702_VL2_MUX 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ZX296702_GL0_MUX 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define ZX296702_GL1_MUX 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define ZX296702_GL2_MUX 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define ZX296702_WB_MUX 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define ZX296702_HDMI_MUX 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ZX296702_VOU_TV_ENC_HD_MUX 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define ZX296702_VOU_TV_ENC_SD_MUX 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ZX296702_VL0_CLK 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ZX296702_VL1_CLK 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define ZX296702_VL2_CLK 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define ZX296702_GL0_CLK 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define ZX296702_GL1_CLK 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define ZX296702_GL2_CLK 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define ZX296702_WB_CLK 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define ZX296702_CL_CLK 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define ZX296702_MAIN_MIX_CLK 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ZX296702_AUX_MIX_CLK 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define ZX296702_HDMI_CLK 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define ZX296702_VOU_TV_ENC_HD_DAC_CLK 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define ZX296702_VOU_TV_ENC_SD_DAC_CLK 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define ZX296702_A9_PERIPHCLK 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define ZX296702_TOPCLK_END 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define ZX296702_SDMMC1_WCLK_MUX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define ZX296702_SDMMC1_WCLK_DIV 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define ZX296702_SDMMC1_WCLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define ZX296702_SDMMC1_PCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define ZX296702_SPDIF0_WCLK_MUX 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define ZX296702_SPDIF0_WCLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define ZX296702_SPDIF0_PCLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define ZX296702_SPDIF0_DIV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define ZX296702_I2S0_WCLK_MUX 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define ZX296702_I2S0_WCLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define ZX296702_I2S0_PCLK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define ZX296702_I2S0_DIV 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define ZX296702_I2S1_WCLK_MUX 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define ZX296702_I2S1_WCLK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define ZX296702_I2S1_PCLK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define ZX296702_I2S1_DIV 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define ZX296702_I2S2_WCLK_MUX 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define ZX296702_I2S2_WCLK 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define ZX296702_I2S2_PCLK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define ZX296702_I2S2_DIV 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define ZX296702_GPIO_CLK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define ZX296702_LSP0CLK_END 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define ZX296702_UART0_WCLK_MUX 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define ZX296702_UART0_WCLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define ZX296702_UART0_PCLK 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define ZX296702_UART1_WCLK_MUX 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define ZX296702_UART1_WCLK 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define ZX296702_UART1_PCLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define ZX296702_SDMMC0_WCLK_MUX 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define ZX296702_SDMMC0_WCLK_DIV 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define ZX296702_SDMMC0_WCLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ZX296702_SDMMC0_PCLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define ZX296702_SPDIF1_WCLK_MUX 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define ZX296702_SPDIF1_WCLK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ZX296702_SPDIF1_PCLK 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define ZX296702_SPDIF1_DIV 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define ZX296702_LSP1CLK_END 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #endif /* __DT_BINDINGS_CLOCK_ZX296702_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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