^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Xilinx Zynq MPSoC Firmware layer
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Copyright (C) 2014-2018 Xilinx, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _DT_BINDINGS_CLK_ZYNQMP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _DT_BINDINGS_CLK_ZYNQMP_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define IOPLL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define RPLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define APLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define DPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define VPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define IOPLL_TO_FPD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define RPLL_TO_FPD 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define APLL_TO_LPD 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define DPLL_TO_LPD 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define VPLL_TO_LPD 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ACPU 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ACPU_HALF 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DBF_FPD 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DBF_LPD 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DBG_TRACE 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DBG_TSTMP 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DP_VIDEO_REF 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DP_AUDIO_REF 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DP_STC_REF 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define GDMA_REF 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DPDMA_REF 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DDR_REF 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SATA_REF 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define PCIE_REF 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define GPU_REF 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define GPU_PP0_REF 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define GPU_PP1_REF 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TOPSW_MAIN 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TOPSW_LSBUS 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define GTGREF0_REF 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define LPD_SWITCH 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define LPD_LSBUS 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define USB0_BUS_REF 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define USB1_BUS_REF 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define USB3_DUAL_REF 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define USB0 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define USB1 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CPU_R5 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CPU_R5_CORE 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CSU_SPB 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CSU_PLL 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCAP 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define IOU_SWITCH 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define GEM_TSU_REF 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define GEM_TSU 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define GEM0_TX 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define GEM1_TX 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define GEM2_TX 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define GEM3_TX 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define GEM0_RX 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define GEM1_RX 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define GEM2_RX 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define GEM3_RX 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define QSPI_REF 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SDIO0_REF 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SDIO1_REF 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define UART0_REF 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define UART1_REF 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SPI0_REF 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SPI1_REF 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define NAND_REF 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define I2C0_REF 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define I2C1_REF 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CAN0_REF 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CAN1_REF 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CAN0 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CAN1 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DLL_REF 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define ADMA_REF 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TIMESTAMP_REF 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define AMS_REF 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PL0_REF 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PL1_REF 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PL2_REF 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PL3_REF 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define WDT 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define IOPLL_INT 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define IOPLL_PRE_SRC 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define IOPLL_HALF 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define IOPLL_INT_MUX 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define IOPLL_POST_SRC 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define RPLL_INT 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define RPLL_PRE_SRC 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define RPLL_HALF 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define RPLL_INT_MUX 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define RPLL_POST_SRC 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define APLL_INT 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define APLL_PRE_SRC 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define APLL_HALF 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define APLL_INT_MUX 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define APLL_POST_SRC 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define DPLL_INT 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define DPLL_PRE_SRC 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define DPLL_HALF 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define DPLL_INT_MUX 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DPLL_POST_SRC 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VPLL_INT 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VPLL_PRE_SRC 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VPLL_HALF 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VPLL_INT_MUX 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VPLL_POST_SRC 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CAN0_MIO 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CAN1_MIO 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ACPU_FULL 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define GEM0_REF 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define GEM1_REF 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define GEM2_REF 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define GEM3_REF 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define GEM0_REF_UNG 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define GEM1_REF_UNG 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define GEM2_REF_UNG 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define GEM3_REF_UNG 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define LPD_WDT 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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