Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides clock numbers for the ingenic,x1830-cgu DT binding.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * They are roughly ordered as:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  *   - external clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *   - PLLs
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  *   - muxes/dividers in the order they appear in the x1830 programmers manual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *   - gates in order of their bit in the CLKGR* registers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef __DT_BINDINGS_CLOCK_X1830_CGU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define __DT_BINDINGS_CLOCK_X1830_CGU_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define X1830_CLK_EXCLK			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define X1830_CLK_RTCLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define X1830_CLK_APLL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define X1830_CLK_MPLL			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define X1830_CLK_EPLL			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define X1830_CLK_VPLL			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define X1830_CLK_OTGPHY		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define X1830_CLK_SCLKA			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define X1830_CLK_CPUMUX		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define X1830_CLK_CPU			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define X1830_CLK_L2CACHE		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define X1830_CLK_AHB0			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define X1830_CLK_AHB2PMUX		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define X1830_CLK_AHB2			13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define X1830_CLK_PCLK			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define X1830_CLK_DDR			15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define X1830_CLK_MAC			16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define X1830_CLK_LCD			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define X1830_CLK_MSCMUX		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define X1830_CLK_MSC0			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define X1830_CLK_MSC1			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define X1830_CLK_SSIPLL		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define X1830_CLK_SSIPLL_DIV2	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define X1830_CLK_SSIMUX		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define X1830_CLK_EMC			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define X1830_CLK_EFUSE			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define X1830_CLK_OTG			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define X1830_CLK_SSI0			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define X1830_CLK_SMB0			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define X1830_CLK_SMB1			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define X1830_CLK_SMB2			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define X1830_CLK_UART0			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define X1830_CLK_UART1			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define X1830_CLK_SSI1			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define X1830_CLK_SFC			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define X1830_CLK_PDMA			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define X1830_CLK_TCU			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define X1830_CLK_DTRNG			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define X1830_CLK_OST			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define X1830_CLK_EXCLK_DIV512	39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define X1830_CLK_RTC			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #endif /* __DT_BINDINGS_CLOCK_X1830_CGU_H__ */