Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright 2013 Freescale Semiconductor, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) #ifndef __DT_BINDINGS_CLOCK_VF610_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #define __DT_BINDINGS_CLOCK_VF610_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define VF610_CLK_DUMMY			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define VF610_CLK_SIRC_128K		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define VF610_CLK_SIRC_32K		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define VF610_CLK_FIRC			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define VF610_CLK_SXOSC			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define VF610_CLK_FXOSC			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define VF610_CLK_FXOSC_HALF		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define VF610_CLK_SLOW_CLK_SEL		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define VF610_CLK_FASK_CLK_SEL		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define VF610_CLK_AUDIO_EXT		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define VF610_CLK_ENET_EXT		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define VF610_CLK_PLL1_SYS		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define VF610_CLK_PLL1_PFD1		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define VF610_CLK_PLL1_PFD2		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define VF610_CLK_PLL1_PFD3		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define VF610_CLK_PLL1_PFD4		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define VF610_CLK_PLL2_BUS		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define VF610_CLK_PLL2_PFD1		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define VF610_CLK_PLL2_PFD2		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define VF610_CLK_PLL2_PFD3		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define VF610_CLK_PLL2_PFD4		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define VF610_CLK_PLL3_USB_OTG		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define VF610_CLK_PLL3_PFD1		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define VF610_CLK_PLL3_PFD2		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define VF610_CLK_PLL3_PFD3		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define VF610_CLK_PLL3_PFD4		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define VF610_CLK_PLL4_AUDIO		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define VF610_CLK_PLL5_ENET		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define VF610_CLK_PLL6_VIDEO		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define VF610_CLK_PLL3_MAIN_DIV		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define VF610_CLK_PLL4_MAIN_DIV		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define VF610_CLK_PLL6_MAIN_DIV		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define VF610_CLK_PLL1_PFD_SEL		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define VF610_CLK_PLL2_PFD_SEL		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define VF610_CLK_SYS_SEL		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define VF610_CLK_DDR_SEL		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define VF610_CLK_SYS_BUS		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define VF610_CLK_PLATFORM_BUS		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define VF610_CLK_IPG_BUS		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define VF610_CLK_UART0			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define VF610_CLK_UART1			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define VF610_CLK_UART2			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define VF610_CLK_UART3			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define VF610_CLK_UART4			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define VF610_CLK_UART5			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define VF610_CLK_PIT			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define VF610_CLK_I2C0			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define VF610_CLK_I2C1			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define VF610_CLK_I2C2			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define VF610_CLK_I2C3			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define VF610_CLK_FTM0_EXT_SEL		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define VF610_CLK_FTM0_FIX_SEL		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define VF610_CLK_FTM0_EXT_FIX_EN	52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define VF610_CLK_FTM1_EXT_SEL		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define VF610_CLK_FTM1_FIX_SEL		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define VF610_CLK_FTM1_EXT_FIX_EN	55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define VF610_CLK_FTM2_EXT_SEL		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define VF610_CLK_FTM2_FIX_SEL		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define VF610_CLK_FTM2_EXT_FIX_EN	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define VF610_CLK_FTM3_EXT_SEL		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define VF610_CLK_FTM3_FIX_SEL		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define VF610_CLK_FTM3_EXT_FIX_EN	61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define VF610_CLK_FTM0			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define VF610_CLK_FTM1			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define VF610_CLK_FTM2			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define VF610_CLK_FTM3			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define VF610_CLK_ENET_50M		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define VF610_CLK_ENET_25M		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define VF610_CLK_ENET_SEL		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define VF610_CLK_ENET			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define VF610_CLK_ENET_TS_SEL		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define VF610_CLK_ENET_TS		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define VF610_CLK_DSPI0			72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define VF610_CLK_DSPI1			73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define VF610_CLK_DSPI2			74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define VF610_CLK_DSPI3			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define VF610_CLK_WDT			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define VF610_CLK_ESDHC0_SEL		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define VF610_CLK_ESDHC0_EN		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define VF610_CLK_ESDHC0_DIV		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define VF610_CLK_ESDHC0		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define VF610_CLK_ESDHC1_SEL		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define VF610_CLK_ESDHC1_EN		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define VF610_CLK_ESDHC1_DIV		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define VF610_CLK_ESDHC1		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define VF610_CLK_DCU0_SEL		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define VF610_CLK_DCU0_EN		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define VF610_CLK_DCU0_DIV		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define VF610_CLK_DCU0			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define VF610_CLK_DCU1_SEL		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define VF610_CLK_DCU1_EN		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define VF610_CLK_DCU1_DIV		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define VF610_CLK_DCU1			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define VF610_CLK_ESAI_SEL		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define VF610_CLK_ESAI_EN		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define VF610_CLK_ESAI_DIV		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define VF610_CLK_ESAI			96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define VF610_CLK_SAI0_SEL		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define VF610_CLK_SAI0_EN		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define VF610_CLK_SAI0_DIV		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define VF610_CLK_SAI0			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define VF610_CLK_SAI1_SEL		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define VF610_CLK_SAI1_EN		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VF610_CLK_SAI1_DIV		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define VF610_CLK_SAI1			104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define VF610_CLK_SAI2_SEL		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define VF610_CLK_SAI2_EN		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define VF610_CLK_SAI2_DIV		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define VF610_CLK_SAI2			108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define VF610_CLK_SAI3_SEL		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define VF610_CLK_SAI3_EN		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define VF610_CLK_SAI3_DIV		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define VF610_CLK_SAI3			112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define VF610_CLK_USBC0			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define VF610_CLK_USBC1			114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define VF610_CLK_QSPI0_SEL		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define VF610_CLK_QSPI0_EN		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define VF610_CLK_QSPI0_X4_DIV		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define VF610_CLK_QSPI0_X2_DIV		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define VF610_CLK_QSPI0_X1_DIV		119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define VF610_CLK_QSPI1_SEL		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define VF610_CLK_QSPI1_EN		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define VF610_CLK_QSPI1_X4_DIV		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define VF610_CLK_QSPI1_X2_DIV		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define VF610_CLK_QSPI1_X1_DIV		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define VF610_CLK_QSPI0			125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define VF610_CLK_QSPI1			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define VF610_CLK_NFC_SEL		127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define VF610_CLK_NFC_EN		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define VF610_CLK_NFC_PRE_DIV		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define VF610_CLK_NFC_FRAC_DIV		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define VF610_CLK_NFC_INV		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define VF610_CLK_NFC			132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define VF610_CLK_VADC_SEL		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define VF610_CLK_VADC_EN		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define VF610_CLK_VADC_DIV		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define VF610_CLK_VADC_DIV_HALF		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define VF610_CLK_VADC			137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define VF610_CLK_ADC0			138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define VF610_CLK_ADC1			139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define VF610_CLK_DAC0			140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define VF610_CLK_DAC1			141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define VF610_CLK_FLEXCAN0		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define VF610_CLK_FLEXCAN1		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define VF610_CLK_ASRC			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define VF610_CLK_GPU_SEL		145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define VF610_CLK_GPU_EN		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define VF610_CLK_GPU2D			147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define VF610_CLK_ENET0			148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define VF610_CLK_ENET1			149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define VF610_CLK_DMAMUX0		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define VF610_CLK_DMAMUX1		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define VF610_CLK_DMAMUX2		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define VF610_CLK_DMAMUX3		153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define VF610_CLK_FLEXCAN0_EN		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define VF610_CLK_FLEXCAN1_EN		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define VF610_CLK_PLL7_USB_HOST		156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define VF610_CLK_USBPHY0		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define VF610_CLK_USBPHY1		158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define VF610_CLK_LVDS1_IN		159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define VF610_CLK_ANACLK1		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define VF610_CLK_PLL1_BYPASS_SRC	161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define VF610_CLK_PLL2_BYPASS_SRC	162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define VF610_CLK_PLL3_BYPASS_SRC	163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define VF610_CLK_PLL4_BYPASS_SRC	164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define VF610_CLK_PLL5_BYPASS_SRC	165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define VF610_CLK_PLL6_BYPASS_SRC	166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define VF610_CLK_PLL7_BYPASS_SRC	167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define VF610_CLK_PLL1			168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define VF610_CLK_PLL2			169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define VF610_CLK_PLL3			170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define VF610_CLK_PLL4			171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define VF610_CLK_PLL5			172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define VF610_CLK_PLL6			173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define VF610_CLK_PLL7			174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define VF610_PLL1_BYPASS		175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define VF610_PLL2_BYPASS		176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define VF610_PLL3_BYPASS		177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define VF610_PLL4_BYPASS		178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define VF610_PLL5_BYPASS		179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define VF610_PLL6_BYPASS		180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define VF610_PLL7_BYPASS		181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define VF610_CLK_SNVS			182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define VF610_CLK_DAP			183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define VF610_CLK_OCOTP			184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define VF610_CLK_DDRMC			185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define VF610_CLK_WKPU			186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define VF610_CLK_TCON0			187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define VF610_CLK_TCON1			188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define VF610_CLK_CAAM			189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define VF610_CLK_CRC			190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define VF610_CLK_END			191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #endif /* __DT_BINDINGS_CLOCK_VF610_H */