Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  * This header provides constants for DRA7 ATL (Audio Tracking Logic)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * The constants defined in this header are used in dts files
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Copyright (C) 2013 Texas Instruments, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8)  * Peter Ujfalusi <peter.ujfalusi@ti.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * This program is free software; you can redistribute it and/or modify
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  * it under the terms of the GNU General Public License version 2 as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * published by the Free Software Foundation.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * This program is distributed "as is" WITHOUT ANY WARRANTY of any
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * kind, whether express or implied; without even the implied warranty
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * of MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #ifndef _DT_BINDINGS_CLK_DRA7_ATL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define _DT_BINDINGS_CLK_DRA7_ATL_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define DRA7_ATL_WS_MCASP1_FSR		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define DRA7_ATL_WS_MCASP1_FSX		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define DRA7_ATL_WS_MCASP2_FSR		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define DRA7_ATL_WS_MCASP2_FSX		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define DRA7_ATL_WS_MCASP3_FSX		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define DRA7_ATL_WS_MCASP4_FSX		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define DRA7_ATL_WS_MCASP5_FSX		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define DRA7_ATL_WS_MCASP6_FSX		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define DRA7_ATL_WS_MCASP7_FSX		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define DRA7_ATL_WS_MCASP8_FSX		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DRA7_ATL_WS_MCASP8_AHCLKX	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define DRA7_ATL_WS_XREF_CLK3		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define DRA7_ATL_WS_XREF_CLK0		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define DRA7_ATL_WS_XREF_CLK1		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define DRA7_ATL_WS_XREF_CLK2		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define DRA7_ATL_WS_OSC1_X1		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #endif