Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This header provides constants for binding nvidia,tegra30-car.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * The first 130 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * this case, those clocks are assigned IDs above 160 in order to highlight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * this issue. Implementations that interpret these clock IDs as bit values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * explicitly handle these special cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * The balance of the clocks controlled by the CAR are assigned IDs of 160 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #ifndef _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define _DT_BINDINGS_CLOCK_TEGRA30_CAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TEGRA30_CLK_CPU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* 3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TEGRA30_CLK_RTC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TEGRA30_CLK_TIMER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TEGRA30_CLK_UARTA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* 7 (register bit affects uartb and vfir) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TEGRA30_CLK_GPIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TEGRA30_CLK_SDMMC2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* 10 (register bit affects spdif_in and spdif_out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TEGRA30_CLK_I2S1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TEGRA30_CLK_I2C1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TEGRA30_CLK_NDFLASH 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TEGRA30_CLK_SDMMC1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TEGRA30_CLK_SDMMC4 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TEGRA30_CLK_PWM 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TEGRA30_CLK_I2S2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TEGRA30_CLK_EPP 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* 20 (register bit affects vi and vi_sensor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define TEGRA30_CLK_GR2D 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TEGRA30_CLK_USBD 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TEGRA30_CLK_ISP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define TEGRA30_CLK_GR3D 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TEGRA30_CLK_DISP2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TEGRA30_CLK_DISP1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TEGRA30_CLK_HOST1X 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TEGRA30_CLK_VCP 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TEGRA30_CLK_I2S0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define TEGRA30_CLK_COP_CACHE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TEGRA30_CLK_MC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TEGRA30_CLK_AHBDMA 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TEGRA30_CLK_APBDMA 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* 35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TEGRA30_CLK_KBC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define TEGRA30_CLK_STATMON 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define TEGRA30_CLK_PMC 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* 39 (register bit affects fuse and fuse_burn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define TEGRA30_CLK_KFUSE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define TEGRA30_CLK_SBC1 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define TEGRA30_CLK_NOR 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* 43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define TEGRA30_CLK_SBC2 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* 45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TEGRA30_CLK_SBC3 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TEGRA30_CLK_I2C5 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TEGRA30_CLK_DSIA 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* 49 (register bit affects cve and tvo) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TEGRA30_CLK_MIPI 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define TEGRA30_CLK_HDMI 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TEGRA30_CLK_CSI 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define TEGRA30_CLK_TVDAC 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define TEGRA30_CLK_I2C2 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define TEGRA30_CLK_UARTC 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) /* 56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define TEGRA30_CLK_EMC 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define TEGRA30_CLK_USB2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define TEGRA30_CLK_USB3 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define TEGRA30_CLK_MPE 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define TEGRA30_CLK_VDE 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define TEGRA30_CLK_BSEA 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define TEGRA30_CLK_BSEV 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define TEGRA30_CLK_SPEEDO 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define TEGRA30_CLK_UARTD 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define TEGRA30_CLK_UARTE 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define TEGRA30_CLK_I2C3 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define TEGRA30_CLK_SBC4 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define TEGRA30_CLK_SDMMC3 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TEGRA30_CLK_PCIE 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TEGRA30_CLK_OWR 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TEGRA30_CLK_AFI 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TEGRA30_CLK_CSITE 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* 74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define TEGRA30_CLK_AVPUCQ 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TEGRA30_CLK_LA 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* 77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* 78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA30_CLK_DTV 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA30_CLK_NDSPEED 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA30_CLK_I2CSLOW 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA30_CLK_DSIB 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* 83 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA30_CLK_IRAMA 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA30_CLK_IRAMB 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA30_CLK_IRAMC 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA30_CLK_IRAMD 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA30_CLK_CRAM2 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) /* 89 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA30_CLK_AUDIO_2X 90 /* a/k/a audio_2x_sync_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* 91 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA30_CLK_CSUS 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA30_CLK_CDEV2 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA30_CLK_CDEV1 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* 95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA30_CLK_CPU_G 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA30_CLK_CPU_LP 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA30_CLK_GR3D2 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA30_CLK_MSELECT 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA30_CLK_TSENSOR 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA30_CLK_I2S3 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA30_CLK_I2S4 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA30_CLK_I2C4 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA30_CLK_SBC5 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA30_CLK_SBC6 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA30_CLK_D_AUDIO 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA30_CLK_APBIF 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA30_CLK_DAM0 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA30_CLK_DAM1 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA30_CLK_DAM2 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA30_CLK_HDA2CODEC_2X 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA30_CLK_ATOMICS 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA30_CLK_AUDIO0_2X 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA30_CLK_AUDIO1_2X 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA30_CLK_AUDIO2_2X 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA30_CLK_AUDIO3_2X 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA30_CLK_AUDIO4_2X 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA30_CLK_SPDIF_2X 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA30_CLK_ACTMON 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA30_CLK_EXTERN1 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA30_CLK_EXTERN2 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA30_CLK_EXTERN3 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA30_CLK_SATA_OOB 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA30_CLK_SATA 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA30_CLK_HDA 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* 126 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA30_CLK_SE 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA30_CLK_HDA2HDMI 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA30_CLK_SATA_COLD 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* 130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* 131 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* 132 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* 133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* 134 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* 135 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA30_CLK_CEC 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* 137 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* 138 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* 139 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* 140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* 141 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* 142 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* 143 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* 144 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) /* 145 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) /* 146 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) /* 147 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* 148 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) /* 149 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) /* 150 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* 151 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* 152 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) /* 153 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* 154 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* 155 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* 156 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) /* 157 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* 158 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* 159 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TEGRA30_CLK_UARTB 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA30_CLK_VFIR 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TEGRA30_CLK_SPDIF_IN 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA30_CLK_SPDIF_OUT 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TEGRA30_CLK_VI 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TEGRA30_CLK_VI_SENSOR 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TEGRA30_CLK_FUSE 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA30_CLK_FUSE_BURN 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TEGRA30_CLK_CVE 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TEGRA30_CLK_TVO 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TEGRA30_CLK_CLK_32K 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TEGRA30_CLK_CLK_M 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TEGRA30_CLK_CLK_M_DIV2 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEGRA30_CLK_CLK_M_DIV4 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TEGRA30_CLK_OSC_DIV2 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TEGRA30_CLK_OSC_DIV4 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TEGRA30_CLK_PLL_REF 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TEGRA30_CLK_PLL_C 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TEGRA30_CLK_PLL_C_OUT1 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA30_CLK_PLL_M 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TEGRA30_CLK_PLL_M_OUT1 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TEGRA30_CLK_PLL_P 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TEGRA30_CLK_PLL_P_OUT1 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TEGRA30_CLK_PLL_P_OUT2 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TEGRA30_CLK_PLL_P_OUT3 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TEGRA30_CLK_PLL_P_OUT4 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TEGRA30_CLK_PLL_A 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TEGRA30_CLK_PLL_A_OUT0 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TEGRA30_CLK_PLL_D 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TEGRA30_CLK_PLL_D_OUT0 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TEGRA30_CLK_PLL_D2 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TEGRA30_CLK_PLL_D2_OUT0 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TEGRA30_CLK_PLL_U 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TEGRA30_CLK_PLL_X 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TEGRA30_CLK_PLL_X_OUT0 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TEGRA30_CLK_PLL_E 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TEGRA30_CLK_SPDIF_IN_SYNC 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TEGRA30_CLK_I2S0_SYNC 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TEGRA30_CLK_I2S1_SYNC 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TEGRA30_CLK_I2S2_SYNC 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TEGRA30_CLK_I2S3_SYNC 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TEGRA30_CLK_I2S4_SYNC 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TEGRA30_CLK_VIMCLK_SYNC 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TEGRA30_CLK_AUDIO0 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TEGRA30_CLK_AUDIO1 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TEGRA30_CLK_AUDIO2 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TEGRA30_CLK_AUDIO3 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TEGRA30_CLK_AUDIO4 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TEGRA30_CLK_SPDIF 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* 207 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) /* 208 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) /* 209 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TEGRA30_CLK_SCLK 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) /* 211 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TEGRA30_CLK_CCLK_G 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TEGRA30_CLK_CCLK_LP 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TEGRA30_CLK_TWD 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TEGRA30_CLK_CML0 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TEGRA30_CLK_CML1 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TEGRA30_CLK_HCLK 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TEGRA30_CLK_PCLK 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) /* 219 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TEGRA30_CLK_OSC 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) /* 221 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) /* 222 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) /* 223 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) /* 288 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) /* 289 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) /* 290 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* 291 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* 292 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) /* 293 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) /* 294 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) /* 295 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) /* 296 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) /* 297 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) /* 298 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* 299 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) /* 300 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) /* 301 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) /* 302 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TEGRA30_CLK_AUDIO0_MUX 303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TEGRA30_CLK_AUDIO1_MUX 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TEGRA30_CLK_AUDIO2_MUX 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TEGRA30_CLK_AUDIO3_MUX 306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TEGRA30_CLK_AUDIO4_MUX 307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TEGRA30_CLK_SPDIF_MUX 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TEGRA30_CLK_CLK_MAX 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #endif	/* _DT_BINDINGS_CLOCK_TEGRA30_CAR_H */