Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /* Copyright (c) 2018-2019, NVIDIA CORPORATION. All rights reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4) #ifndef DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) #define DT_BINDINGS_CLOCK_TEGRA234_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) /** @brief output of gate CLK_ENB_FUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define TEGRA234_CLK_FUSE			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define TEGRA234_CLK_SDMMC4			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TEGRA234_CLK_UARTA			155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #endif