Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This header provides constants for binding nvidia,tegra210-car.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * The first 224 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * this case, those clocks are assigned IDs above 224 in order to highlight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * this issue. Implementations that interpret these clock IDs as bit values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * explicitly handle these special cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  * The balance of the clocks controlled by the CAR are assigned IDs of 224 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #ifndef _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define _DT_BINDINGS_CLOCK_TEGRA210_CAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TEGRA210_CLK_ISPB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TEGRA210_CLK_RTC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TEGRA210_CLK_TIMER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TEGRA210_CLK_UARTA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) /* 7 (register bit affects uartb and vfir) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define TEGRA210_CLK_GPIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define TEGRA210_CLK_SDMMC2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) /* 10 (register bit affects spdif_in and spdif_out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define TEGRA210_CLK_I2S1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TEGRA210_CLK_I2C1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) /* 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define TEGRA210_CLK_SDMMC1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TEGRA210_CLK_SDMMC4 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define TEGRA210_CLK_PWM 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TEGRA210_CLK_I2S2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) /* 19 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* 20 (register bit affects vi and vi_sensor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TEGRA210_CLK_USBD 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TEGRA210_CLK_ISPA 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* 24 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TEGRA210_CLK_DISP2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TEGRA210_CLK_DISP1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TEGRA210_CLK_HOST1X 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) /* 29 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TEGRA210_CLK_I2S0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TEGRA210_CLK_MC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define TEGRA210_CLK_AHBDMA 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TEGRA210_CLK_APBDMA 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* 35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) /* 36 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define TEGRA210_CLK_PMC 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* 39 (register bit affects fuse and fuse_burn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define TEGRA210_CLK_KFUSE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define TEGRA210_CLK_SBC1 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) /* 42 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* 43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define TEGRA210_CLK_SBC2 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* 45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TEGRA210_CLK_SBC3 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TEGRA210_CLK_I2C5 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TEGRA210_CLK_DSIA 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* 49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) /* 50 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) /* 51 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TEGRA210_CLK_CSI 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* 53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define TEGRA210_CLK_I2C2 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define TEGRA210_CLK_UARTC 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define TEGRA210_CLK_MIPI_CAL 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define TEGRA210_CLK_EMC 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define TEGRA210_CLK_USB2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) /* 59 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* 60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) /* 61 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) /* 62 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define TEGRA210_CLK_BSEV 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define TEGRA210_CLK_UARTD 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* 66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define TEGRA210_CLK_I2C3 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define TEGRA210_CLK_SBC4 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define TEGRA210_CLK_SDMMC3 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TEGRA210_CLK_PCIE 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TEGRA210_CLK_OWR 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TEGRA210_CLK_AFI 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TEGRA210_CLK_CSITE 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* 74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* 75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TEGRA210_CLK_LA 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) /* 77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA210_CLK_SOC_THERM 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA210_CLK_DTV 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* 80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA210_CLK_I2CSLOW 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA210_CLK_DSIB 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA210_CLK_TSEC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* 84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* 85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* 86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* 87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* 88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA210_CLK_XUSB_HOST 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* 90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* 91 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA210_CLK_CSUS 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 93 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* 94 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* 95 (bit affects xusb_dev and xusb_dev_src) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* 96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* 97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* 98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA210_CLK_MSELECT 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA210_CLK_TSENSOR 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA210_CLK_I2S3 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA210_CLK_I2S4 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA210_CLK_I2C4 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) /* 104 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* 105 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA210_CLK_D_AUDIO 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA210_CLK_APB2APE 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) /* 108 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) /* 109 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) /* 110 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA210_CLK_HDA2CODEC_2X 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* 112 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) /* 113 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) /* 114 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* 115 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) /* 116 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) /* 117 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA210_CLK_SPDIF_2X 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA210_CLK_ACTMON 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA210_CLK_EXTERN1 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA210_CLK_EXTERN2 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA210_CLK_EXTERN3 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA210_CLK_SATA_OOB 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA210_CLK_SATA 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA210_CLK_HDA 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* 126 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) /* 127 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA210_CLK_HDA2HDMI 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) /* 129 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* 130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* 131 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* 132 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* 133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* 134 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* 135 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA210_CLK_CEC 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* 137 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* 138 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* 139 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* 140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* 141 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* 142 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* (bit affects xusb_falcon_src, xusb_fs_src, xusb_host_src and xusb_ss_src) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TEGRA210_CLK_XUSB_GATE 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TEGRA210_CLK_CILAB 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA210_CLK_CILCD 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TEGRA210_CLK_CILE 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA210_CLK_DSIALP 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TEGRA210_CLK_DSIBLP 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA210_CLK_ENTROPY 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) /* 150 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* 151 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TEGRA210_CLK_DP2 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* 153 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) /* 154 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* 155 (bit affects dfll_ref and dfll_soc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TEGRA210_CLK_XUSB_SS 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* 157 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* 158 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* 159 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* 160 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TEGRA210_CLK_DMIC1 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA210_CLK_DMIC2 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* 163 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* 164 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* 165 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA210_CLK_I2C6 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* 167 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* 168 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* 169 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* 170 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TEGRA210_CLK_VIM2_CLK 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* 172 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TEGRA210_CLK_MIPIBIF 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* 174 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* 175 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* 176 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TEGRA210_CLK_CLK72MHZ 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA210_CLK_VIC03 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* 179 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) /* 180 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TEGRA210_CLK_DPAUX 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TEGRA210_CLK_SOR0 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TEGRA210_CLK_SOR1 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TEGRA210_CLK_GPU 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TEGRA210_CLK_DBGAPB 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* 186 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TEGRA210_CLK_PLL_P_OUT_ADSP 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* 188 ((bit affects pll_a_out_adsp and pll_a_out0_out_adsp)*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TEGRA210_CLK_PLL_G_REF 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* 190 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* 191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) /* 192 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TEGRA210_CLK_SDMMC_LEGACY 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TEGRA210_CLK_NVDEC 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TEGRA210_CLK_NVJPG 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) /* 196 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TEGRA210_CLK_DMIC3 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TEGRA210_CLK_APE 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TEGRA210_CLK_ADSP 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* 200 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) /* 201 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TEGRA210_CLK_MAUD 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) /* 203 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* 204 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) /* 205 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TEGRA210_CLK_TSECB 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TEGRA210_CLK_DPAUX1 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TEGRA210_CLK_VI_I2C 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TEGRA210_CLK_HSIC_TRK 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TEGRA210_CLK_USB2_TRK 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TEGRA210_CLK_QSPI 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TEGRA210_CLK_UARTAPE 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) /* 213 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) /* 214 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) /* 215 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) /* 216 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) /* 217 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TEGRA210_CLK_ADSP_NEON 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TEGRA210_CLK_NVENC 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TEGRA210_CLK_IQC2 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TEGRA210_CLK_IQC1 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TEGRA210_CLK_SOR_SAFE 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TEGRA210_CLK_PLL_P_OUT_CPU 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TEGRA210_CLK_UARTB 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TEGRA210_CLK_VFIR 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TEGRA210_CLK_SPDIF_IN 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TEGRA210_CLK_SPDIF_OUT 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TEGRA210_CLK_VI 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TEGRA210_CLK_VI_SENSOR 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TEGRA210_CLK_FUSE 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TEGRA210_CLK_FUSE_BURN 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TEGRA210_CLK_CLK_32K 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TEGRA210_CLK_CLK_M 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TEGRA210_CLK_CLK_M_DIV2 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TEGRA210_CLK_CLK_M_DIV4 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TEGRA210_CLK_OSC_DIV2 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TEGRA210_CLK_OSC_DIV4 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TEGRA210_CLK_PLL_REF 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TEGRA210_CLK_PLL_C 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TEGRA210_CLK_PLL_C_OUT1 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TEGRA210_CLK_PLL_C2 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TEGRA210_CLK_PLL_C3 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TEGRA210_CLK_PLL_M 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TEGRA210_CLK_PLL_M_OUT1 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TEGRA210_CLK_PLL_P 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TEGRA210_CLK_PLL_P_OUT1 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TEGRA210_CLK_PLL_P_OUT2 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define TEGRA210_CLK_PLL_P_OUT3 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TEGRA210_CLK_PLL_P_OUT4 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define TEGRA210_CLK_PLL_A 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define TEGRA210_CLK_PLL_A_OUT0 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TEGRA210_CLK_PLL_D 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TEGRA210_CLK_PLL_D_OUT0 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TEGRA210_CLK_PLL_D2 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TEGRA210_CLK_PLL_D2_OUT0 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TEGRA210_CLK_PLL_U 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TEGRA210_CLK_PLL_U_480M 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TEGRA210_CLK_PLL_U_60M 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TEGRA210_CLK_PLL_U_48M 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) /* 258 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TEGRA210_CLK_PLL_X 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TEGRA210_CLK_PLL_X_OUT0 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TEGRA210_CLK_PLL_RE_VCO 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TEGRA210_CLK_PLL_RE_OUT 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TEGRA210_CLK_PLL_E 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TEGRA210_CLK_SPDIF_IN_SYNC 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TEGRA210_CLK_I2S0_SYNC 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define TEGRA210_CLK_I2S1_SYNC 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define TEGRA210_CLK_I2S2_SYNC 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TEGRA210_CLK_I2S3_SYNC 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define TEGRA210_CLK_I2S4_SYNC 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TEGRA210_CLK_VIMCLK_SYNC 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TEGRA210_CLK_AUDIO0 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define TEGRA210_CLK_AUDIO1 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TEGRA210_CLK_AUDIO2 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define TEGRA210_CLK_AUDIO3 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define TEGRA210_CLK_AUDIO4 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TEGRA210_CLK_SPDIF 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* 277 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* 278 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* 279 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* 280 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define TEGRA210_CLK_SOR0_LVDS 281 /* deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define TEGRA210_CLK_SOR0_OUT 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define TEGRA210_CLK_SOR1_OUT 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* 283 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TEGRA210_CLK_XUSB_HOST_SRC 284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TEGRA210_CLK_XUSB_FALCON_SRC 285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TEGRA210_CLK_XUSB_FS_SRC 286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define TEGRA210_CLK_XUSB_SS_SRC 287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define TEGRA210_CLK_XUSB_DEV_SRC 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define TEGRA210_CLK_XUSB_DEV 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define TEGRA210_CLK_XUSB_HS_SRC 290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define TEGRA210_CLK_SCLK 291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define TEGRA210_CLK_HCLK 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define TEGRA210_CLK_PCLK 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define TEGRA210_CLK_CCLK_G 294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define TEGRA210_CLK_CCLK_LP 295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define TEGRA210_CLK_DFLL_REF 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TEGRA210_CLK_DFLL_SOC 297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TEGRA210_CLK_VI_SENSOR2 298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define TEGRA210_CLK_PLL_P_OUT5 299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define TEGRA210_CLK_CML0 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define TEGRA210_CLK_CML1 301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define TEGRA210_CLK_PLL_C4 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define TEGRA210_CLK_PLL_DP 303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define TEGRA210_CLK_PLL_E_MUX 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define TEGRA210_CLK_PLL_MB 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define TEGRA210_CLK_PLL_A1 306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define TEGRA210_CLK_PLL_D_DSI_OUT 307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define TEGRA210_CLK_PLL_C4_OUT0 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TEGRA210_CLK_PLL_C4_OUT1 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define TEGRA210_CLK_PLL_C4_OUT2 310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define TEGRA210_CLK_PLL_C4_OUT3 311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define TEGRA210_CLK_PLL_U_OUT 312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define TEGRA210_CLK_PLL_U_OUT1 313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define TEGRA210_CLK_PLL_U_OUT2 314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define TEGRA210_CLK_USB2_HSIC_TRK 315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define TEGRA210_CLK_PLL_P_OUT_HSIO 316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define TEGRA210_CLK_PLL_P_OUT_XUSB 317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define TEGRA210_CLK_XUSB_SSP_SRC 318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define TEGRA210_CLK_PLL_RE_OUT1 319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define TEGRA210_CLK_PLL_MB_UD 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define TEGRA210_CLK_PLL_P_UD 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define TEGRA210_CLK_ISP 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define TEGRA210_CLK_PLL_A_OUT_ADSP 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define TEGRA210_CLK_PLL_A_OUT0_OUT_ADSP 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* 325 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define TEGRA210_CLK_OSC 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TEGRA210_CLK_CSI_TPG 327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /* 328 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) /* 329 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /* 330 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) /* 331 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /* 332 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) /* 333 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /* 334 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) /* 335 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /* 336 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) /* 337 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /* 338 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) /* 339 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /* 340 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) /* 341 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /* 342 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* 343 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /* 344 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) /* 345 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /* 346 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) /* 347 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /* 348 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) /* 349 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define TEGRA210_CLK_AUDIO0_MUX 350
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define TEGRA210_CLK_AUDIO1_MUX 351
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define TEGRA210_CLK_AUDIO2_MUX 352
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define TEGRA210_CLK_AUDIO3_MUX 353
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define TEGRA210_CLK_AUDIO4_MUX 354
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define TEGRA210_CLK_SPDIF_MUX 355
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) /* 356 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /* 357 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) /* 358 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define TEGRA210_CLK_DSIA_MUX 359
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define TEGRA210_CLK_DSIB_MUX 360
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /* 361 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TEGRA210_CLK_XUSB_SS_DIV2 362
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define TEGRA210_CLK_PLL_M_UD 363
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define TEGRA210_CLK_PLL_C_UD 364
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define TEGRA210_CLK_SCLK_MUX 365
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define TEGRA210_CLK_ACLK 370
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define TEGRA210_CLK_DMIC1_SYNC_CLK 388
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define TEGRA210_CLK_DMIC1_SYNC_CLK_MUX 389
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define TEGRA210_CLK_DMIC2_SYNC_CLK 390
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define TEGRA210_CLK_DMIC2_SYNC_CLK_MUX 391
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define TEGRA210_CLK_DMIC3_SYNC_CLK 392
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define TEGRA210_CLK_DMIC3_SYNC_CLK_MUX 393
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define TEGRA210_CLK_CLK_MAX 394
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #endif	/* _DT_BINDINGS_CLOCK_TEGRA210_CAR_H */