^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * This header provides constants for binding nvidia,tegra20-car.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * The first 96 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * registers. These IDs often match those in the CAR's RST_DEVICES registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * this case, those clocks are assigned IDs above 95 in order to highlight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * this issue. Implementations that interpret these clock IDs as bit values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * explicitly handle these special cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * The balance of the clocks controlled by the CAR are assigned IDs of 96 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #ifndef _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define _DT_BINDINGS_CLOCK_TEGRA20_CAR_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA20_CLK_CPU 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA20_CLK_AC97 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA20_CLK_RTC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA20_CLK_TIMER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA20_CLK_UARTA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* 7 (register bit affects uart2 and vfir) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA20_CLK_GPIO 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA20_CLK_SDMMC2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* 10 (register bit affects spdif_in and spdif_out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA20_CLK_I2S1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA20_CLK_I2C1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA20_CLK_NDFLASH 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA20_CLK_SDMMC1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA20_CLK_SDMMC4 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA20_CLK_TWC 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA20_CLK_PWM 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA20_CLK_I2S2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA20_CLK_EPP 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* 20 (register bit affects vi and vi_sensor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA20_CLK_GR2D 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA20_CLK_USBD 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA20_CLK_ISP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA20_CLK_GR3D 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA20_CLK_IDE 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA20_CLK_DISP2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA20_CLK_DISP1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA20_CLK_HOST1X 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA20_CLK_VCP 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* 30 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEGRA20_CLK_CACHE2 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA20_CLK_MC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA20_CLK_AHBDMA 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA20_CLK_APBDMA 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* 35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEGRA20_CLK_KBC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA20_CLK_STAT_MON 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEGRA20_CLK_PMC 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEGRA20_CLK_FUSE 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA20_CLK_KFUSE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA20_CLK_SBC1 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEGRA20_CLK_NOR 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA20_CLK_SPI 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA20_CLK_SBC2 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA20_CLK_XIO 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA20_CLK_SBC3 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA20_CLK_DVC 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA20_CLK_DSI 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) /* 49 (register bit affects tvo and cve) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA20_CLK_MIPI 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEGRA20_CLK_HDMI 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA20_CLK_CSI 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA20_CLK_TVDAC 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TEGRA20_CLK_I2C2 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA20_CLK_UARTC 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) /* 56 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TEGRA20_CLK_EMC 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA20_CLK_USB2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA20_CLK_USB3 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TEGRA20_CLK_MPE 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA20_CLK_VDE 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA20_CLK_BSEA 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TEGRA20_CLK_BSEV 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEGRA20_CLK_SPEEDO 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TEGRA20_CLK_UARTD 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA20_CLK_UARTE 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TEGRA20_CLK_I2C3 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEGRA20_CLK_SBC4 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TEGRA20_CLK_SDMMC3 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEGRA20_CLK_PEX 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TEGRA20_CLK_OWR 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TEGRA20_CLK_AFI 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TEGRA20_CLK_CSITE 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) /* 74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TEGRA20_CLK_AVPUCQ 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TEGRA20_CLK_LA 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) /* 77 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) /* 78 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) /* 79 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* 80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* 81 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) /* 82 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) /* 83 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA20_CLK_IRAMA 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA20_CLK_IRAMB 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA20_CLK_IRAMC 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA20_CLK_IRAMD 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA20_CLK_CRAM2 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA20_CLK_AUDIO_2X 89 /* a/k/a audio_2x_sync_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA20_CLK_CLK_D 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) /* 91 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA20_CLK_CSUS 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA20_CLK_CDEV2 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA20_CLK_CDEV1 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* 95 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA20_CLK_UARTB 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA20_CLK_VFIR 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA20_CLK_SPDIF_IN 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA20_CLK_SPDIF_OUT 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA20_CLK_VI 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA20_CLK_VI_SENSOR 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA20_CLK_TVO 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA20_CLK_CVE 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA20_CLK_OSC 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA20_CLK_CLK_32K 105 /* a/k/a clk_s */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA20_CLK_CLK_M 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA20_CLK_SCLK 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA20_CLK_CCLK 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA20_CLK_HCLK 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA20_CLK_PCLK 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) /* 111 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA20_CLK_PLL_A 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA20_CLK_PLL_A_OUT0 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA20_CLK_PLL_C 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA20_CLK_PLL_C_OUT1 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA20_CLK_PLL_D 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA20_CLK_PLL_D_OUT0 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA20_CLK_PLL_E 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA20_CLK_PLL_M 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA20_CLK_PLL_M_OUT1 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA20_CLK_PLL_P 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA20_CLK_PLL_P_OUT1 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA20_CLK_PLL_P_OUT2 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA20_CLK_PLL_P_OUT3 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA20_CLK_PLL_P_OUT4 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TEGRA20_CLK_PLL_S 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA20_CLK_PLL_U 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA20_CLK_PLL_X 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA20_CLK_COP 129 /* a/k/a avp */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEGRA20_CLK_AUDIO 130 /* a/k/a audio_sync_clk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TEGRA20_CLK_PLL_REF 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TEGRA20_CLK_TWD 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TEGRA20_CLK_CLK_MAX 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #endif /* _DT_BINDINGS_CLOCK_TEGRA20_CAR_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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