^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /* Copyright (c) 2018, NVIDIA CORPORATION. All rights reserved. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef __ABI_MACH_T194_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define __ABI_MACH_T194_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define TEGRA194_CLK_ACTMON 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define TEGRA194_CLK_ADSP 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define TEGRA194_CLK_ADSPNEON 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define TEGRA194_CLK_AHUB 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define TEGRA194_CLK_APB2APE 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define TEGRA194_CLK_APE 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define TEGRA194_CLK_AUD_MCLK 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define TEGRA194_CLK_AXI_CBB 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define TEGRA194_CLK_CAN1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define TEGRA194_CLK_CAN1_HOST 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define TEGRA194_CLK_CAN2 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define TEGRA194_CLK_CAN2_HOST 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define TEGRA194_CLK_CEC 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define TEGRA194_CLK_CLK_M 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define TEGRA194_CLK_DMIC1 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define TEGRA194_CLK_DMIC2 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define TEGRA194_CLK_DMIC3 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define TEGRA194_CLK_DMIC4 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define TEGRA194_CLK_DPAUX 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define TEGRA194_CLK_DPAUX1 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define TEGRA194_CLK_ACLK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define TEGRA194_CLK_MSS_ENCRYPT 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define TEGRA194_CLK_EQOS_RX_INPUT 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define TEGRA194_CLK_IQC2 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define TEGRA194_CLK_AON_APB 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TEGRA194_CLK_AON_NIC 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define TEGRA194_CLK_AON_CPU_NIC 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define TEGRA194_CLK_PLLA1 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define TEGRA194_CLK_DSPK1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define TEGRA194_CLK_DSPK2 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define TEGRA194_CLK_EMC 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define TEGRA194_CLK_EQOS_AXI 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define TEGRA194_CLK_EQOS_PTP_REF 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define TEGRA194_CLK_EQOS_RX 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define TEGRA194_CLK_EQOS_TX 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define TEGRA194_CLK_EXTPERIPH1 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define TEGRA194_CLK_EXTPERIPH2 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define TEGRA194_CLK_EXTPERIPH3 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define TEGRA194_CLK_EXTPERIPH4 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define TEGRA194_CLK_FUSE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define TEGRA194_CLK_GPCCLK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define TEGRA194_CLK_GPU_PWR 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define TEGRA194_CLK_HDA 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define TEGRA194_CLK_HDA2CODEC_2X 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define TEGRA194_CLK_HDA2HDMICODEC 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define TEGRA194_CLK_HOST1X 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define TEGRA194_CLK_HSIC_TRK 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define TEGRA194_CLK_I2C1 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define TEGRA194_CLK_I2C2 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define TEGRA194_CLK_I2C3 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define TEGRA194_CLK_I2C4 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define TEGRA194_CLK_I2C6 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define TEGRA194_CLK_I2C7 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define TEGRA194_CLK_I2C8 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define TEGRA194_CLK_I2C9 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define TEGRA194_CLK_I2S1 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define TEGRA194_CLK_I2S1_SYNC_INPUT 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define TEGRA194_CLK_I2S2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define TEGRA194_CLK_I2S2_SYNC_INPUT 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define TEGRA194_CLK_I2S3 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define TEGRA194_CLK_I2S3_SYNC_INPUT 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define TEGRA194_CLK_I2S4 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define TEGRA194_CLK_I2S4_SYNC_INPUT 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define TEGRA194_CLK_I2S5 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define TEGRA194_CLK_I2S5_SYNC_INPUT 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define TEGRA194_CLK_I2S6 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define TEGRA194_CLK_I2S6_SYNC_INPUT 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define TEGRA194_CLK_IQC1 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define TEGRA194_CLK_ISP 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define TEGRA194_CLK_KFUSE 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define TEGRA194_CLK_MAUD 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define TEGRA194_CLK_MIPI_CAL 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define TEGRA194_CLK_MPHY_CORE_PLL_FIXED 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define TEGRA194_CLK_MPHY_L0_RX_ANA 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define TEGRA194_CLK_MPHY_L0_RX_LS_BIT 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define TEGRA194_CLK_MPHY_L0_RX_SYMB 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define TEGRA194_CLK_MPHY_L0_TX_LS_3XBIT 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define TEGRA194_CLK_MPHY_L0_TX_SYMB 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define TEGRA194_CLK_MPHY_L1_RX_ANA 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define TEGRA194_CLK_MPHY_TX_1MHZ_REF 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define TEGRA194_CLK_NVCSI 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define TEGRA194_CLK_NVCSILP 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define TEGRA194_CLK_NVDEC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define TEGRA194_CLK_NVDISPLAYHUB 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define TEGRA194_CLK_NVDISPLAY_DISP 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define TEGRA194_CLK_NVDISPLAY_P0 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TEGRA194_CLK_NVDISPLAY_P1 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TEGRA194_CLK_NVDISPLAY_P2 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TEGRA194_CLK_NVENC 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TEGRA194_CLK_NVJPG 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TEGRA194_CLK_OSC 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TEGRA194_CLK_AON_TOUCH 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TEGRA194_CLK_PLLA 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA194_CLK_PLLAON 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA194_CLK_PLLD 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define TEGRA194_CLK_PLLD2 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA194_CLK_PLLD3 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA194_CLK_PLLDP 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA194_CLK_PLLD4 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TEGRA194_CLK_PLLE 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TEGRA194_CLK_PLLP 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TEGRA194_CLK_PLLP_OUT0 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TEGRA194_CLK_UTMIPLL 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TEGRA194_CLK_PLLA_OUT0 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA194_CLK_PWM1 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define TEGRA194_CLK_PWM2 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA194_CLK_PWM3 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA194_CLK_PWM4 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define TEGRA194_CLK_PWM5 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define TEGRA194_CLK_PWM6 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define TEGRA194_CLK_PWM7 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define TEGRA194_CLK_PWM8 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define TEGRA194_CLK_RCE_CPU_NIC 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define TEGRA194_CLK_RCE_NIC 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define TEGRA194_CLK_SATA 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA194_CLK_SATA_OOB 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA194_CLK_AON_I2C_SLOW 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA194_CLK_SCE_CPU_NIC 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA194_CLK_SCE_NIC 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA194_CLK_SDMMC1 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA194_CLK_UPHY_PLL3 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA194_CLK_SDMMC3 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA194_CLK_SDMMC4 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA194_CLK_SE 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA194_CLK_SOR0_OUT 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA194_CLK_SOR0_REF 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA194_CLK_SOR0_PAD_CLKOUT 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA194_CLK_SOR1_OUT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define TEGRA194_CLK_SOR1_REF 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA194_CLK_SOR1_PAD_CLKOUT 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA194_CLK_SOR_SAFE 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA194_CLK_IQC1_IN 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA194_CLK_IQC2_IN 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA194_CLK_DMIC5 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA194_CLK_SPI1 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA194_CLK_SPI2 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA194_CLK_SPI3 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA194_CLK_I2C_SLOW 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA194_CLK_SYNC_DMIC1 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA194_CLK_SYNC_DMIC2 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA194_CLK_SYNC_DMIC3 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA194_CLK_SYNC_DMIC4 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define TEGRA194_CLK_SYNC_DSPK1 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA194_CLK_SYNC_DSPK2 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define TEGRA194_CLK_SYNC_I2S1 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA194_CLK_SYNC_I2S2 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA194_CLK_SYNC_I2S3 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define TEGRA194_CLK_SYNC_I2S4 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define TEGRA194_CLK_SYNC_I2S5 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define TEGRA194_CLK_SYNC_I2S6 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define TEGRA194_CLK_MPHY_FORCE_LS_MODE 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define TEGRA194_CLK_TACH 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define TEGRA194_CLK_TSEC 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA194_CLK_TSECB 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define TEGRA194_CLK_UARTA 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define TEGRA194_CLK_UARTB 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define TEGRA194_CLK_UARTC 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define TEGRA194_CLK_UARTD 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define TEGRA194_CLK_UARTE 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define TEGRA194_CLK_UARTF 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define TEGRA194_CLK_UARTG 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define TEGRA194_CLK_UART_FST_MIPI_CAL 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TEGRA194_CLK_UFSDEV_REF 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA194_CLK_UFSHC 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TEGRA194_CLK_USB2_TRK 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA194_CLK_VI 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TEGRA194_CLK_VIC 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA194_CLK_PVA0_AXI 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TEGRA194_CLK_PVA0_VPS0 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define TEGRA194_CLK_PVA0_VPS1 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TEGRA194_CLK_PVA1_AXI 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TEGRA194_CLK_PVA1_VPS0 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TEGRA194_CLK_PVA1_VPS1 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define TEGRA194_CLK_DLA0_FALCON 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TEGRA194_CLK_DLA0_CORE 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define TEGRA194_CLK_DLA1_FALCON 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define TEGRA194_CLK_DLA1_CORE 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define TEGRA194_CLK_SOR2_OUT 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define TEGRA194_CLK_SOR2_REF 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define TEGRA194_CLK_SOR2_PAD_CLKOUT 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define TEGRA194_CLK_SOR3_OUT 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define TEGRA194_CLK_SOR3_REF 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define TEGRA194_CLK_SOR3_PAD_CLKOUT 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define TEGRA194_CLK_NVDISPLAY_P3 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define TEGRA194_CLK_DPAUX2 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA194_CLK_DPAUX3 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define TEGRA194_CLK_NVDEC1 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define TEGRA194_CLK_NVENC1 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define TEGRA194_CLK_SE_FREE 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define TEGRA194_CLK_UARTH 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TEGRA194_CLK_FUSE_SERIAL 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define TEGRA194_CLK_QSPI0 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define TEGRA194_CLK_QSPI1 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define TEGRA194_CLK_QSPI0_PM 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define TEGRA194_CLK_QSPI1_PM 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TEGRA194_CLK_VI_CONST 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TEGRA194_CLK_NAFLL_BPMP 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA194_CLK_NAFLL_SCE 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define TEGRA194_CLK_NAFLL_NVDEC 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TEGRA194_CLK_NAFLL_NVJPG 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TEGRA194_CLK_NAFLL_TSEC 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TEGRA194_CLK_NAFLL_TSECB 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define TEGRA194_CLK_NAFLL_VI 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TEGRA194_CLK_NAFLL_SE 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TEGRA194_CLK_NAFLL_NVENC 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TEGRA194_CLK_NAFLL_ISP 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TEGRA194_CLK_NAFLL_VIC 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TEGRA194_CLK_NAFLL_NVDISPLAYHUB 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TEGRA194_CLK_NAFLL_AXICBB 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TEGRA194_CLK_NAFLL_DLA 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TEGRA194_CLK_NAFLL_PVA_CORE 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TEGRA194_CLK_NAFLL_PVA_VPS 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TEGRA194_CLK_NAFLL_CVNAS 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TEGRA194_CLK_NAFLL_RCE 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TEGRA194_CLK_NAFLL_NVENC1 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TEGRA194_CLK_NAFLL_DLA_FALCON 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TEGRA194_CLK_NAFLL_NVDEC1 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TEGRA194_CLK_NAFLL_GPU 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TEGRA194_CLK_SDMMC_LEGACY_TM 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TEGRA194_CLK_PEX0_CORE_0 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TEGRA194_CLK_PEX0_CORE_1 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TEGRA194_CLK_PEX0_CORE_2 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TEGRA194_CLK_PEX0_CORE_3 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TEGRA194_CLK_PEX0_CORE_4 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TEGRA194_CLK_PEX1_CORE_5 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TEGRA194_CLK_PEX_REF1 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TEGRA194_CLK_PEX_REF2 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TEGRA194_CLK_CSI_A 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TEGRA194_CLK_CSI_B 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TEGRA194_CLK_CSI_C 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TEGRA194_CLK_CSI_D 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TEGRA194_CLK_CSI_E 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TEGRA194_CLK_CSI_F 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TEGRA194_CLK_CSI_G 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TEGRA194_CLK_CSI_H 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TEGRA194_CLK_PLLC4 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TEGRA194_CLK_PLLC4_OUT 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TEGRA194_CLK_PLLC4_OUT1 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TEGRA194_CLK_PLLC4_OUT2 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TEGRA194_CLK_PLLC4_MUXED 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TEGRA194_CLK_PLLC4_VCO_DIV2 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TEGRA194_CLK_CSI_A_PAD 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TEGRA194_CLK_CSI_B_PAD 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TEGRA194_CLK_CSI_C_PAD 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TEGRA194_CLK_CSI_D_PAD 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define TEGRA194_CLK_CSI_E_PAD 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TEGRA194_CLK_CSI_F_PAD 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TEGRA194_CLK_CSI_G_PAD 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TEGRA194_CLK_CSI_H_PAD 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define TEGRA194_CLK_PEX_SATA_USB_RX_BYP 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define TEGRA194_CLK_PEX_USB_PAD_PLL0_MGMT 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TEGRA194_CLK_PEX_USB_PAD_PLL1_MGMT 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TEGRA194_CLK_PEX_USB_PAD_PLL2_MGMT 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TEGRA194_CLK_PEX_USB_PAD_PLL3_MGMT 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TEGRA194_CLK_XUSB_CORE_DEV 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TEGRA194_CLK_XUSB_CORE_MUX 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TEGRA194_CLK_XUSB_CORE_HOST 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TEGRA194_CLK_XUSB_CORE_SS 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TEGRA194_CLK_XUSB_FALCON 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TEGRA194_CLK_XUSB_FALCON_HOST 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TEGRA194_CLK_XUSB_FALCON_SS 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TEGRA194_CLK_XUSB_FS 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TEGRA194_CLK_XUSB_FS_HOST 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TEGRA194_CLK_XUSB_FS_DEV 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TEGRA194_CLK_XUSB_SS 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TEGRA194_CLK_XUSB_SS_DEV 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TEGRA194_CLK_XUSB_SS_SUPERSPEED 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define TEGRA194_CLK_PLLDISPHUB 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define TEGRA194_CLK_PLLDISPHUB_DIV 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define TEGRA194_CLK_NAFLL_CLUSTER0 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define TEGRA194_CLK_NAFLL_CLUSTER1 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TEGRA194_CLK_NAFLL_CLUSTER2 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define TEGRA194_CLK_NAFLL_CLUSTER3 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define TEGRA194_CLK_CAN1_CORE 284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TEGRA194_CLK_CAN2_CORE 285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TEGRA194_CLK_PLLA1_OUT1 286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TEGRA194_CLK_PLLREFE_VCOOUT 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TEGRA194_CLK_CLK_32K 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define TEGRA194_CLK_SPDIFIN_SYNC_INPUT 290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TEGRA194_CLK_UTMIPLL_CLKOUT48 291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TEGRA194_CLK_UTMIPLL_CLKOUT480 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TEGRA194_CLK_CVNAS 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TEGRA194_CLK_PLLNVCSI 294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TEGRA194_CLK_PVA0_CPU_AXI 295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TEGRA194_CLK_PVA1_CPU_AXI 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define TEGRA194_CLK_PVA0_VPS 297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define TEGRA194_CLK_PVA1_VPS 298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TEGRA194_CLK_DLA0_FALCON_MUX 299
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TEGRA194_CLK_DLA1_FALCON_MUX 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TEGRA194_CLK_DLA0_CORE_MUX 301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TEGRA194_CLK_DLA1_CORE_MUX 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define TEGRA194_CLK_UTMIPLL_HPS 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define TEGRA194_CLK_I2C5 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TEGRA194_CLK_I2C10 306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define TEGRA194_CLK_BPMP_CPU_NIC 307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TEGRA194_CLK_BPMP_APB 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TEGRA194_CLK_TSC 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define TEGRA194_CLK_EMCSA 310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define TEGRA194_CLK_EMCSB 311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define TEGRA194_CLK_EMCSC 312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define TEGRA194_CLK_EMCSD 313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define TEGRA194_CLK_PLLC 314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define TEGRA194_CLK_PLLC2 315
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define TEGRA194_CLK_PLLC3 316
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define TEGRA194_CLK_TSC_REF 317
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define TEGRA194_CLK_FUSE_BURN 318
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define TEGRA194_CLK_PEX0_CORE_0M 319
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define TEGRA194_CLK_PEX0_CORE_1M 320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define TEGRA194_CLK_PEX0_CORE_2M 321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define TEGRA194_CLK_PEX0_CORE_3M 322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define TEGRA194_CLK_PEX0_CORE_4M 323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define TEGRA194_CLK_PEX1_CORE_5M 324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define TEGRA194_CLK_PLLE_HPS 326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags