^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /** @file */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #ifndef _MACH_T186_CLK_T186_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define _MACH_T186_CLK_T186_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * @defgroup clock_ids Clock Identifiers
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * @defgroup extern_input external input clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * @def TEGRA186_CLK_OSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * @def TEGRA186_CLK_CLK_32K
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * @def TEGRA186_CLK_DTV_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * @def TEGRA186_CLK_SOR0_PAD_CLKOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * @def TEGRA186_CLK_SOR1_PAD_CLKOUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * @def TEGRA186_CLK_I2S1_SYNC_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) * @def TEGRA186_CLK_I2S2_SYNC_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * @def TEGRA186_CLK_I2S3_SYNC_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) * @def TEGRA186_CLK_I2S4_SYNC_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * @def TEGRA186_CLK_I2S5_SYNC_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * @def TEGRA186_CLK_I2S6_SYNC_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * @def TEGRA186_CLK_SPDIFIN_SYNC_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * @defgroup extern_output external output clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * @def TEGRA186_CLK_EXTPERIPH1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) * @def TEGRA186_CLK_EXTPERIPH2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * @def TEGRA186_CLK_EXTPERIPH3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * @def TEGRA186_CLK_EXTPERIPH4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * @defgroup display_clks display related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * @def TEGRA186_CLK_CEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * @def TEGRA186_CLK_DSIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * @def TEGRA186_CLK_DSIC_LP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * @def TEGRA186_CLK_DSID
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) * @def TEGRA186_CLK_DSID_LP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) * @def TEGRA186_CLK_DPAUX1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) * @def TEGRA186_CLK_DPAUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) * @def TEGRA186_CLK_HDA2HDMICODEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) * @def TEGRA186_CLK_NVDISPLAY_DISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) * @def TEGRA186_CLK_NVDISPLAY_DSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) * @def TEGRA186_CLK_NVDISPLAY_P0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) * @def TEGRA186_CLK_NVDISPLAY_P1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) * @def TEGRA186_CLK_NVDISPLAY_P2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) * @def TEGRA186_CLK_NVDISPLAYHUB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) * @def TEGRA186_CLK_SOR_SAFE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) * @def TEGRA186_CLK_SOR0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) * @def TEGRA186_CLK_SOR0_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) * @def TEGRA186_CLK_SOR1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) * @def TEGRA186_CLK_SOR1_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) * @def TEGRA186_CLK_DSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) * @def TEGRA186_CLK_MIPI_CAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) * @def TEGRA186_CLK_DSIA_LP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) * @def TEGRA186_CLK_DSIB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) * @def TEGRA186_CLK_DSIB_LP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) * @defgroup camera_clks camera related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) * @def TEGRA186_CLK_NVCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) * @def TEGRA186_CLK_NVCSILP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) * @def TEGRA186_CLK_VI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) * @defgroup audio_clks audio related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) * @def TEGRA186_CLK_ACLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) * @def TEGRA186_CLK_ADSP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) * @def TEGRA186_CLK_ADSPNEON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) * @def TEGRA186_CLK_AHUB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) * @def TEGRA186_CLK_APE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) * @def TEGRA186_CLK_APB2APE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) * @def TEGRA186_CLK_AUD_MCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) * @def TEGRA186_CLK_DMIC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) * @def TEGRA186_CLK_DMIC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) * @def TEGRA186_CLK_DMIC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) * @def TEGRA186_CLK_DMIC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) * @def TEGRA186_CLK_DSPK1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) * @def TEGRA186_CLK_DSPK2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) * @def TEGRA186_CLK_HDA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) * @def TEGRA186_CLK_HDA2CODEC_2X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) * @def TEGRA186_CLK_I2S1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) * @def TEGRA186_CLK_I2S2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) * @def TEGRA186_CLK_I2S3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) * @def TEGRA186_CLK_I2S4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) * @def TEGRA186_CLK_I2S5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) * @def TEGRA186_CLK_I2S6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) * @def TEGRA186_CLK_MAUD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) * @def TEGRA186_CLK_PLL_A_OUT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) * @def TEGRA186_CLK_SPDIF_DOUBLER
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) * @def TEGRA186_CLK_SPDIF_IN
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) * @def TEGRA186_CLK_SPDIF_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) * @def TEGRA186_CLK_SYNC_DMIC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) * @def TEGRA186_CLK_SYNC_DMIC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) * @def TEGRA186_CLK_SYNC_DMIC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) * @def TEGRA186_CLK_SYNC_DMIC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) * @def TEGRA186_CLK_SYNC_DMIC5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) * @def TEGRA186_CLK_SYNC_DSPK1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) * @def TEGRA186_CLK_SYNC_DSPK2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) * @def TEGRA186_CLK_SYNC_I2S1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) * @def TEGRA186_CLK_SYNC_I2S2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) * @def TEGRA186_CLK_SYNC_I2S3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) * @def TEGRA186_CLK_SYNC_I2S4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) * @def TEGRA186_CLK_SYNC_I2S5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) * @def TEGRA186_CLK_SYNC_I2S6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) * @def TEGRA186_CLK_SYNC_SPDIF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) * @defgroup uart_clks UART clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) * @def TEGRA186_CLK_AON_UART_FST_MIPI_CAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) * @def TEGRA186_CLK_UARTA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) * @def TEGRA186_CLK_UARTB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) * @def TEGRA186_CLK_UARTC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) * @def TEGRA186_CLK_UARTD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) * @def TEGRA186_CLK_UARTE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) * @def TEGRA186_CLK_UARTF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) * @def TEGRA186_CLK_UARTG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) * @def TEGRA186_CLK_UART_FST_MIPI_CAL
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) * @defgroup i2c_clks I2C clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) * @def TEGRA186_CLK_AON_I2C_SLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) * @def TEGRA186_CLK_I2C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) * @def TEGRA186_CLK_I2C2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) * @def TEGRA186_CLK_I2C3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) * @def TEGRA186_CLK_I2C4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) * @def TEGRA186_CLK_I2C5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) * @def TEGRA186_CLK_I2C6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) * @def TEGRA186_CLK_I2C8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) * @def TEGRA186_CLK_I2C9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) * @def TEGRA186_CLK_I2C1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) * @def TEGRA186_CLK_I2C12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) * @def TEGRA186_CLK_I2C13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) * @def TEGRA186_CLK_I2C14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) * @def TEGRA186_CLK_I2C_SLOW
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) * @def TEGRA186_CLK_VI_I2C
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) * @defgroup spi_clks SPI clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) * @def TEGRA186_CLK_SPI1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) * @def TEGRA186_CLK_SPI2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) * @def TEGRA186_CLK_SPI3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) * @def TEGRA186_CLK_SPI4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) * @defgroup storage storage related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) * @def TEGRA186_CLK_SATA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) * @def TEGRA186_CLK_SATA_OOB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) * @def TEGRA186_CLK_SATA_IOBIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) * @def TEGRA186_CLK_SDMMC_LEGACY_TM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) * @def TEGRA186_CLK_SDMMC1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) * @def TEGRA186_CLK_SDMMC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) * @def TEGRA186_CLK_SDMMC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) * @def TEGRA186_CLK_SDMMC4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) * @def TEGRA186_CLK_QSPI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) * @def TEGRA186_CLK_QSPI_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) * @def TEGRA186_CLK_UFSDEV_REF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) * @def TEGRA186_CLK_UFSHC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) * @defgroup pwm_clks PWM clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) * @def TEGRA186_CLK_PWM1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) * @def TEGRA186_CLK_PWM2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) * @def TEGRA186_CLK_PWM3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) * @def TEGRA186_CLK_PWM4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) * @def TEGRA186_CLK_PWM5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) * @def TEGRA186_CLK_PWM6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) * @def TEGRA186_CLK_PWM7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) * @def TEGRA186_CLK_PWM8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) * @defgroup plls PLLs and related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) * @def TEGRA186_CLK_PLLREFE_OUT_GATED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) * @def TEGRA186_CLK_PLLREFE_OUT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) * @def TEGRA186_CLK_PLLD_OUT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) * @def TEGRA186_CLK_PLLP_OUT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) * @def TEGRA186_CLK_PLLP_OUT5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) * @def TEGRA186_CLK_PLLA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) * @def TEGRA186_CLK_PLLE_PWRSEQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) * @def TEGRA186_CLK_PLLA_OUT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) * @def TEGRA186_CLK_PLLREFE_REF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) * @def TEGRA186_CLK_UPHY_PLL0_PWRSEQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) * @def TEGRA186_CLK_UPHY_PLL1_PWRSEQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) * @def TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) * @def TEGRA186_CLK_PLLREFE_PEX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) * @def TEGRA186_CLK_PLLREFE_IDDQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) * @def TEGRA186_CLK_PLLC_OUT_AON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) * @def TEGRA186_CLK_PLLC_OUT_ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) * @def TEGRA186_CLK_PLLC_OUT_VE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) * @def TEGRA186_CLK_PLLC4_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) * @def TEGRA186_CLK_PLLREFE_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) * @def TEGRA186_CLK_PLLREFE_PLL_REF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) * @def TEGRA186_CLK_PLLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) * @def TEGRA186_CLK_PLLC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) * @def TEGRA186_CLK_PLLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) * @def TEGRA186_CLK_PLLD
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) * @def TEGRA186_CLK_PLLD2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) * @def TEGRA186_CLK_PLLREFE_VCO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) * @def TEGRA186_CLK_PLLC2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) * @def TEGRA186_CLK_PLLC3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) * @def TEGRA186_CLK_PLLDP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) * @def TEGRA186_CLK_PLLC4_VCO
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) * @def TEGRA186_CLK_PLLA1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) * @def TEGRA186_CLK_PLLNVCSI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) * @def TEGRA186_CLK_PLLDISPHUB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) * @def TEGRA186_CLK_PLLD3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) * @def TEGRA186_CLK_PLLBPMPCAM
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) * @def TEGRA186_CLK_PLLAON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) * @def TEGRA186_CLK_PLLU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) * @def TEGRA186_CLK_PLLC4_VCO_DIV2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) * @def TEGRA186_CLK_PLL_REF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) * @def TEGRA186_CLK_PLLREFE_OUT1_DIV5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) * @def TEGRA186_CLK_UTMIP_PLL_PWRSEQ
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) * @def TEGRA186_CLK_PLL_U_48M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) * @def TEGRA186_CLK_PLL_U_480M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) * @def TEGRA186_CLK_PLLC4_OUT0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) * @def TEGRA186_CLK_PLLC4_OUT1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) * @def TEGRA186_CLK_PLLC4_OUT2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) * @def TEGRA186_CLK_PLLC4_OUT_MUX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) * @def TEGRA186_CLK_DFLLDISP_DIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) * @def TEGRA186_CLK_PLLDISPHUB_DIV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) * @def TEGRA186_CLK_PLLP_DIV8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) * @defgroup nafll_clks NAFLL clock sources
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) * @def TEGRA186_CLK_NAFLL_AXI_CBB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) * @def TEGRA186_CLK_NAFLL_BCPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) * @def TEGRA186_CLK_NAFLL_BPMP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) * @def TEGRA186_CLK_NAFLL_DISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) * @def TEGRA186_CLK_NAFLL_GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) * @def TEGRA186_CLK_NAFLL_ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) * @def TEGRA186_CLK_NAFLL_MCPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) * @def TEGRA186_CLK_NAFLL_NVDEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) * @def TEGRA186_CLK_NAFLL_NVENC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) * @def TEGRA186_CLK_NAFLL_NVJPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) * @def TEGRA186_CLK_NAFLL_SCE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) * @def TEGRA186_CLK_NAFLL_SE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) * @def TEGRA186_CLK_NAFLL_TSEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) * @def TEGRA186_CLK_NAFLL_TSECB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) * @def TEGRA186_CLK_NAFLL_VI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) * @def TEGRA186_CLK_NAFLL_VIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) * @defgroup mphy MPHY related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) * @def TEGRA186_CLK_MPHY_L0_RX_SYMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) * @def TEGRA186_CLK_MPHY_L0_RX_LS_BIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) * @def TEGRA186_CLK_MPHY_L0_TX_SYMB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) * @def TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) * @def TEGRA186_CLK_MPHY_L0_RX_ANA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) * @def TEGRA186_CLK_MPHY_L1_RX_ANA
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) * @def TEGRA186_CLK_MPHY_IOBIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) * @def TEGRA186_CLK_MPHY_TX_1MHZ_REF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) * @def TEGRA186_CLK_MPHY_CORE_PLL_FIXED
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) * @defgroup eavb EAVB related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) * @def TEGRA186_CLK_EQOS_AXI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) * @def TEGRA186_CLK_EQOS_PTP_REF
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) * @def TEGRA186_CLK_EQOS_RX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) * @def TEGRA186_CLK_EQOS_RX_INPUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) * @def TEGRA186_CLK_EQOS_TX
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) * @defgroup usb USB related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) * @def TEGRA186_CLK_PEX_USB_PAD0_MGMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) * @def TEGRA186_CLK_PEX_USB_PAD1_MGMT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) * @def TEGRA186_CLK_HSIC_TRK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) * @def TEGRA186_CLK_USB2_TRK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) * @def TEGRA186_CLK_USB2_HSIC_TRK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) * @def TEGRA186_CLK_XUSB_CORE_SS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) * @def TEGRA186_CLK_XUSB_CORE_DEV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) * @def TEGRA186_CLK_XUSB_FALCON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) * @def TEGRA186_CLK_XUSB_FS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) * @def TEGRA186_CLK_XUSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) * @def TEGRA186_CLK_XUSB_DEV
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) * @def TEGRA186_CLK_XUSB_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) * @def TEGRA186_CLK_XUSB_SS
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) * @defgroup bigblock compute block related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) * @def TEGRA186_CLK_GPCCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) * @def TEGRA186_CLK_GPC2CLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) * @def TEGRA186_CLK_GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) * @def TEGRA186_CLK_HOST1X
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) * @def TEGRA186_CLK_ISP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) * @def TEGRA186_CLK_NVDEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) * @def TEGRA186_CLK_NVENC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) * @def TEGRA186_CLK_NVJPG
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) * @def TEGRA186_CLK_SE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) * @def TEGRA186_CLK_TSEC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) * @def TEGRA186_CLK_TSECB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) * @def TEGRA186_CLK_VIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) * @defgroup can CAN bus related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) * @def TEGRA186_CLK_CAN1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) * @def TEGRA186_CLK_CAN1_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) * @def TEGRA186_CLK_CAN2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) * @def TEGRA186_CLK_CAN2_HOST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) * @defgroup system basic system clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) * @def TEGRA186_CLK_ACTMON
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) * @def TEGRA186_CLK_AON_APB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) * @def TEGRA186_CLK_AON_CPU_NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) * @def TEGRA186_CLK_AON_NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) * @def TEGRA186_CLK_AXI_CBB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) * @def TEGRA186_CLK_BPMP_APB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) * @def TEGRA186_CLK_BPMP_CPU_NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) * @def TEGRA186_CLK_BPMP_NIC_RATE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) * @def TEGRA186_CLK_CLK_M
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) * @def TEGRA186_CLK_EMC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) * @def TEGRA186_CLK_MSS_ENCRYPT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) * @def TEGRA186_CLK_SCE_APB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) * @def TEGRA186_CLK_SCE_CPU_NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) * @def TEGRA186_CLK_SCE_NIC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) * @def TEGRA186_CLK_TSC
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) * @defgroup pcie_clks PCIe related clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) * @{
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) * @def TEGRA186_CLK_AFI
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) * @def TEGRA186_CLK_PCIE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) * @def TEGRA186_CLK_PCIE2_IOBIST
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) * @def TEGRA186_CLK_PCIERX0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) * @def TEGRA186_CLK_PCIERX1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) * @def TEGRA186_CLK_PCIERX2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) * @def TEGRA186_CLK_PCIERX3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) * @def TEGRA186_CLK_PCIERX4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) * @}
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) /** @brief output of gate CLK_ENB_FUSE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define TEGRA186_CLK_FUSE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) * @brief It's not what you think
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) * @details output of gate CLK_ENB_GPU. This output connects to the GPU
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) * pwrclk. @warning: This is almost certainly not the clock you think
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) * it is. If you're looking for the clock of the graphics engine, see
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) * TEGRA186_GPCCLK
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define TEGRA186_CLK_GPU 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) /** @brief output of gate CLK_ENB_PCIE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) #define TEGRA186_CLK_PCIE 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) /** @brief output of the divider IPFS_CLK_DIVISOR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define TEGRA186_CLK_AFI 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) /** @brief output of gate CLK_ENB_PCIE2_IOBIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define TEGRA186_CLK_PCIE2_IOBIST 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) /** @brief output of gate CLK_ENB_PCIERX0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define TEGRA186_CLK_PCIERX0 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) /** @brief output of gate CLK_ENB_PCIERX1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define TEGRA186_CLK_PCIERX1 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) /** @brief output of gate CLK_ENB_PCIERX2*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define TEGRA186_CLK_PCIERX2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) /** @brief output of gate CLK_ENB_PCIERX3*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define TEGRA186_CLK_PCIERX3 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) /** @brief output of gate CLK_ENB_PCIERX4*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define TEGRA186_CLK_PCIERX4 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) /** @brief output branch of PLL_C for ISP, controlled by gate CLK_ENB_PLLC_OUT_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define TEGRA186_CLK_PLLC_OUT_ISP 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) /** @brief output branch of PLL_C for VI, controlled by gate CLK_ENB_PLLC_OUT_VE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define TEGRA186_CLK_PLLC_OUT_VE 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) /** @brief output branch of PLL_C for AON domain, controlled by gate CLK_ENB_PLLC_OUT_AON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define TEGRA186_CLK_PLLC_OUT_AON 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) /** @brief output of gate CLK_ENB_SOR_SAFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define TEGRA186_CLK_SOR_SAFE 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define TEGRA186_CLK_I2S2 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define TEGRA186_CLK_I2S3 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDF_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define TEGRA186_CLK_SPDIF_IN 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /** @brief output of gate CLK_ENB_SPDIF_DOUBLER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define TEGRA186_CLK_SPDIF_DOUBLER 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) /** @clkdesc{spi_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_SPI3} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define TEGRA186_CLK_SPI3 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C1} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define TEGRA186_CLK_I2C1 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) /** @clkdesc{i2c_clks, out, mux, CLK_RST_CONTROLLER_CLK_SOURCE_I2C5} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define TEGRA186_CLK_I2C5 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define TEGRA186_CLK_SPI1 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define TEGRA186_CLK_ISP 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define TEGRA186_CLK_VI 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define TEGRA186_CLK_SDMMC1 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define TEGRA186_CLK_SDMMC2 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define TEGRA186_CLK_SDMMC4 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define TEGRA186_CLK_UARTA 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define TEGRA186_CLK_UARTB 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HOST1X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define TEGRA186_CLK_HOST1X 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) * @brief controls the EMC clock frequency.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) * @details Doing a clk_set_rate on this clock will select the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) * appropriate clock source, program the source rate and execute a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) * specific sequence to switch to the new clock source for both memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) * controllers. This can be used to control the balance between memory
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) * throughput and memory controller power.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) #define TEGRA186_CLK_EMC 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) /* @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define TEGRA186_CLK_EXTPERIPH4 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define TEGRA186_CLK_SPI4 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define TEGRA186_CLK_I2C3 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define TEGRA186_CLK_SDMMC3 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define TEGRA186_CLK_UARTD 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define TEGRA186_CLK_I2S1 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) /** output of gate CLK_ENB_DTV */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define TEGRA186_CLK_DTV 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439) /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) #define TEGRA186_CLK_TSEC 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) /** @brief output of gate CLK_ENB_DP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define TEGRA186_CLK_DP2 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define TEGRA186_CLK_I2S4 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2S5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define TEGRA186_CLK_I2S5 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define TEGRA186_CLK_I2C4 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AHUB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define TEGRA186_CLK_AHUB 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA2CODEC_2X */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define TEGRA186_CLK_HDA2CODEC_2X 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define TEGRA186_CLK_EXTPERIPH1 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456) #define TEGRA186_CLK_EXTPERIPH2 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_EXTPERIPH3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define TEGRA186_CLK_EXTPERIPH3 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C_SLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define TEGRA186_CLK_I2C_SLOW 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) /** @brief output of the SOR1_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define TEGRA186_CLK_SOR1 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) /** @brief output of gate CLK_ENB_CEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define TEGRA186_CLK_CEC 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) /** @brief output of gate CLK_ENB_DPAUX1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define TEGRA186_CLK_DPAUX1 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) /** @brief output of gate CLK_ENB_DPAUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define TEGRA186_CLK_DPAUX 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) /** @brief output of the SOR0_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define TEGRA186_CLK_SOR0 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) /** @brief output of gate CLK_ENB_HDA2HDMICODEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define TEGRA186_CLK_HDA2HDMICODEC 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SATA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) #define TEGRA186_CLK_SATA 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) /** @brief output of gate CLK_ENB_SATA_OOB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define TEGRA186_CLK_SATA_OOB 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) /** @brief output of gate CLK_ENB_SATA_IOBIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define TEGRA186_CLK_SATA_IOBIST 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_HDA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define TEGRA186_CLK_HDA 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define TEGRA186_CLK_SE 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) /** @brief output of gate CLK_ENB_APB2APE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define TEGRA186_CLK_APB2APE 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_APE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define TEGRA186_CLK_APE 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487) /** @brief output of gate CLK_ENB_IQC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) #define TEGRA186_CLK_IQC1 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) /** @brief output of gate CLK_ENB_IQC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define TEGRA186_CLK_IQC2 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) /** divide by 2 version of TEGRA186_CLK_PLLREFE_VCO */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define TEGRA186_CLK_PLLREFE_OUT 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) /** @brief output of gate CLK_ENB_PLLREFE_PLL_REF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define TEGRA186_CLK_PLLREFE_PLL_REF 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) /** @brief output of gate CLK_ENB_PLLC4_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define TEGRA186_CLK_PLLC4_OUT 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) /** @brief output of mux xusb_core_clk_switch on page 67 of T186_Clocks_IAS.doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define TEGRA186_CLK_XUSB 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) /** controls xusb_dev_ce signal on page 66 and 67 of T186_Clocks_IAS.doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define TEGRA186_CLK_XUSB_DEV 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) /** controls xusb_host_ce signal on page 67 of T186_Clocks_IAS.doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define TEGRA186_CLK_XUSB_HOST 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) /** controls xusb_ss_ce signal on page 67 of T186_Clocks_IAS.doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504) #define TEGRA186_CLK_XUSB_SS 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /** @brief output of gate CLK_ENB_DSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define TEGRA186_CLK_DSI 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) /** @brief output of gate CLK_ENB_MIPI_CAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define TEGRA186_CLK_MIPI_CAL 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIA_LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define TEGRA186_CLK_DSIA_LP 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) /** @brief output of gate CLK_ENB_DSIB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define TEGRA186_CLK_DSIB 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIB_LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define TEGRA186_CLK_DSIB_LP 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define TEGRA186_CLK_DMIC1 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define TEGRA186_CLK_DMIC2 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AUD_MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define TEGRA186_CLK_AUD_MCLK 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522) #define TEGRA186_CLK_I2C6 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /**output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UART_FST_MIPI_CAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define TEGRA186_CLK_UART_FST_MIPI_CAL 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define TEGRA186_CLK_VIC 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SDMMC_LEGACY_TM */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define TEGRA186_CLK_SDMMC_LEGACY_TM 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define TEGRA186_CLK_NVDEC 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVJPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define TEGRA186_CLK_NVJPG 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVENC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define TEGRA186_CLK_NVENC 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) /** @brief output of the QSPI_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define TEGRA186_CLK_QSPI 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_VI_I2C */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define TEGRA186_CLK_VI_I2C 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539) /** @brief output of gate CLK_ENB_HSIC_TRK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) #define TEGRA186_CLK_HSIC_TRK 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) /** @brief output of gate CLK_ENB_USB2_TRK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define TEGRA186_CLK_USB2_TRK 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) /** output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MAUD */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define TEGRA186_CLK_MAUD 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSECB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define TEGRA186_CLK_TSECB 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) /** @brief output of gate CLK_ENB_ADSP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define TEGRA186_CLK_ADSP 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) /** @brief output of gate CLK_ENB_ADSPNEON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define TEGRA186_CLK_ADSPNEON 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_RX_LS_SYMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define TEGRA186_CLK_MPHY_L0_RX_SYMB 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) /** @brief output of gate CLK_ENB_MPHY_L0_RX_LS_BIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_L0_TX_LS_SYMB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define TEGRA186_CLK_MPHY_L0_TX_SYMB 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557) /** @brief output of gate CLK_ENB_MPHY_L0_TX_LS_3XBIT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) #define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) /** @brief output of gate CLK_ENB_MPHY_L0_RX_ANA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define TEGRA186_CLK_MPHY_L0_RX_ANA 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) /** @brief output of gate CLK_ENB_MPHY_L1_RX_ANA */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define TEGRA186_CLK_MPHY_L1_RX_ANA 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_IOBIST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define TEGRA186_CLK_MPHY_IOBIST 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_TX_1MHZ_REF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_MPHY_CORE_PLL_FIXED */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AXI_CBB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define TEGRA186_CLK_AXI_CBB 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572) #define TEGRA186_CLK_DMIC3 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define TEGRA186_CLK_DMIC4 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define TEGRA186_CLK_DSPK1 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSPK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define TEGRA186_CLK_DSPK2 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define TEGRA186_CLK_I2S6 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define TEGRA186_CLK_NVDISPLAY_P0 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) /** @brief output of the NVDISPLAY_DISP_CLK_SRC mux in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define TEGRA186_CLK_NVDISPLAY_DISP 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) /** @brief output of gate CLK_ENB_NVDISPLAY_DSC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define TEGRA186_CLK_NVDISPLAY_DSC 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAYHUB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) #define TEGRA186_CLK_NVDISPLAYHUB 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define TEGRA186_CLK_NVDISPLAY_P1 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_P2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define TEGRA186_CLK_NVDISPLAY_P2 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TACH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define TEGRA186_CLK_TACH 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) /** @brief output of gate CLK_ENB_EQOS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define TEGRA186_CLK_EQOS_AXI 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) /** @brief output of gate CLK_ENB_EQOS_RX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define TEGRA186_CLK_EQOS_RX 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSHC_CG_SYS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define TEGRA186_CLK_UFSHC 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UFSDEV_REF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) #define TEGRA186_CLK_UFSDEV_REF 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define TEGRA186_CLK_NVCSI 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_NVCSILP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define TEGRA186_CLK_NVCSILP 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define TEGRA186_CLK_I2C7 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define TEGRA186_CLK_I2C9 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define TEGRA186_CLK_I2C12 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define TEGRA186_CLK_I2C13 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define TEGRA186_CLK_I2C14 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618) #define TEGRA186_CLK_PWM1 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define TEGRA186_CLK_PWM2 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define TEGRA186_CLK_PWM3 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define TEGRA186_CLK_PWM5 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define TEGRA186_CLK_PWM6 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define TEGRA186_CLK_PWM7 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define TEGRA186_CLK_PWM8 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632) #define TEGRA186_CLK_UARTE 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 634) #define TEGRA186_CLK_UARTF 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 635) /** @deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 636) #define TEGRA186_CLK_DBGAPB 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 637) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_CPU_NIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 638) #define TEGRA186_CLK_BPMP_CPU_NIC 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 639) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_BPMP_APB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 640) #define TEGRA186_CLK_BPMP_APB 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 641) /** @brief output of mux controlled by TEGRA186_CLK_SOC_ACTMON */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 642) #define TEGRA186_CLK_ACTMON 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 643) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_CPU_NIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 644) #define TEGRA186_CLK_AON_CPU_NIC 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 645) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 646) #define TEGRA186_CLK_CAN1 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 647) /** @brief output of gate CLK_ENB_CAN1_HOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 648) #define TEGRA186_CLK_CAN1_HOST 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 649) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_CAN2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 650) #define TEGRA186_CLK_CAN2 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 651) /** @brief output of gate CLK_ENB_CAN2_HOST */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 652) #define TEGRA186_CLK_CAN2_HOST 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 653) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_APB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 654) #define TEGRA186_CLK_AON_APB 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 655) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 656) #define TEGRA186_CLK_UARTC 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 657) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_UARTG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 658) #define TEGRA186_CLK_UARTG 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 659) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_UART_FST_MIPI_CAL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 660) #define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 661) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 662) #define TEGRA186_CLK_I2C2 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 663) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 664) #define TEGRA186_CLK_I2C8 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 665) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_I2C10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 666) #define TEGRA186_CLK_I2C10 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 667) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_I2C_SLOW */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 668) #define TEGRA186_CLK_AON_I2C_SLOW 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 669) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPI2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 670) #define TEGRA186_CLK_SPI2 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 671) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DMIC5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 672) #define TEGRA186_CLK_DMIC5 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 673) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_AON_TOUCH */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 674) #define TEGRA186_CLK_AON_TOUCH 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 675) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_PWM4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 676) #define TEGRA186_CLK_PWM4 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 677) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_TSC. This clock object is read only and is used for all timers in the system. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 678) #define TEGRA186_CLK_TSC 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 679) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_MSS_ENCRYPT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 680) #define TEGRA186_CLK_MSS_ENCRYPT 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 681) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_CPU_NIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 682) #define TEGRA186_CLK_SCE_CPU_NIC 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 683) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SCE_APB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 684) #define TEGRA186_CLK_SCE_APB 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 685) /** @brief output of gate CLK_ENB_DSIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 686) #define TEGRA186_CLK_DSIC 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 687) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSIC_LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 688) #define TEGRA186_CLK_DSIC_LP 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 689) /** @brief output of gate CLK_ENB_DSID */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 690) #define TEGRA186_CLK_DSID 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 691) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_DSID_LP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 692) #define TEGRA186_CLK_DSID_LP 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 693) /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_SATA_USB_RX_BYP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 694) #define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 695) /** @brief output of mux controlled by CLK_RST_CONTROLLER_CLK_SOURCE_SPDIF_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 696) #define TEGRA186_CLK_SPDIF_OUT 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 697) /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_PTP_REF_CLK_0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 698) #define TEGRA186_CLK_EQOS_PTP_REF 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 699) /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_EQOS_TX_CLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 700) #define TEGRA186_CLK_EQOS_TX 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 701) /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_USB2_HSIC_TRK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 702) #define TEGRA186_CLK_USB2_HSIC_TRK 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 703) /** @brief output of mux xusb_ss_clk_switch on page 66 of T186_Clocks_IAS.doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 704) #define TEGRA186_CLK_XUSB_CORE_SS 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 705) /** @brief output of mux xusb_core_dev_clk_switch on page 67 of T186_Clocks_IAS.doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 706) #define TEGRA186_CLK_XUSB_CORE_DEV 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 707) /** @brief output of mux xusb_core_falcon_clk_switch on page 67 of T186_Clocks_IAS.doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 708) #define TEGRA186_CLK_XUSB_FALCON 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 709) /** @brief output of mux xusb_fs_clk_switch on page 66 of T186_Clocks_IAS.doc */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 710) #define TEGRA186_CLK_XUSB_FS 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 711) /** @brief output of the divider CLK_RST_CONTROLLER_PLLA_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 712) #define TEGRA186_CLK_PLL_A_OUT0 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 713) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 714) #define TEGRA186_CLK_SYNC_I2S1 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 715) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 716) #define TEGRA186_CLK_SYNC_I2S2 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 717) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 718) #define TEGRA186_CLK_SYNC_I2S3 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 719) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 720) #define TEGRA186_CLK_SYNC_I2S4 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 721) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 722) #define TEGRA186_CLK_SYNC_I2S5 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 723) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_I2S6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 724) #define TEGRA186_CLK_SYNC_I2S6 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 725) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 726) #define TEGRA186_CLK_SYNC_DSPK1 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 727) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DSPK2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 728) #define TEGRA186_CLK_SYNC_DSPK2 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 729) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 730) #define TEGRA186_CLK_SYNC_DMIC1 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 731) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 732) #define TEGRA186_CLK_SYNC_DMIC2 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 733) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 734) #define TEGRA186_CLK_SYNC_DMIC3 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 735) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_DMIC4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 736) #define TEGRA186_CLK_SYNC_DMIC4 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 737) /** @brief output of mux controlled by CLK_RST_CONTROLLER_AUDIO_SYNC_CLK_SPDIF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 738) #define TEGRA186_CLK_SYNC_SPDIF 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 739) /** @brief output of gate CLK_ENB_PLLREFE_OUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 740) #define TEGRA186_CLK_PLLREFE_OUT_GATED 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 741) /** @brief output of the divider PLLREFE_DIVP in CLK_RST_CONTROLLER_PLLREFE_BASE. PLLREFE has 2 outputs:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 742) * * VCO/pdiv defined by this clock object
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 743) * * VCO/2 defined by TEGRA186_CLK_PLLREFE_OUT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 744) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 745) #define TEGRA186_CLK_PLLREFE_OUT1 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 746) #define TEGRA186_CLK_PLLD_OUT1 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 747) /** @brief output of the divider PLLP_DIVP in CLK_RST_CONTROLLER_PLLP_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 748) #define TEGRA186_CLK_PLLP_OUT0 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 749) /** @brief output of the divider CLK_RST_CONTROLLER_PLLP_OUTC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 750) #define TEGRA186_CLK_PLLP_OUT5 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 751) /** PLL controlled by CLK_RST_CONTROLLER_PLLA_BASE for use by audio clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 752) #define TEGRA186_CLK_PLLA 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 753) /** @brief output of mux controlled by CLK_RST_CONTROLLER_ACLK_BURST_POLICY divided by the divider controlled by ACLK_CLK_DIVISOR in CLK_RST_CONTROLLER_SUPER_ACLK_DIVIDER */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 754) #define TEGRA186_CLK_ACLK 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 755) /** fixed 48MHz clock divided down from TEGRA186_CLK_PLL_U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 756) #define TEGRA186_CLK_PLL_U_48M 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 757) /** fixed 480MHz clock divided down from TEGRA186_CLK_PLL_U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 758) #define TEGRA186_CLK_PLL_U_480M 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 759) /** @brief output of the divider PLLC4_DIVP in CLK_RST_CONTROLLER_PLLC4_BASE. Output frequency is TEGRA186_CLK_PLLC4_VCO/PLLC4_DIVP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 760) #define TEGRA186_CLK_PLLC4_OUT0 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 761) /** fixed /3 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 762) #define TEGRA186_CLK_PLLC4_OUT1 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 763) /** fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLC4_VCO/5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 764) #define TEGRA186_CLK_PLLC4_OUT2 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 765) /** @brief output of mux controlled by PLLC4_CLK_SEL in CLK_RST_CONTROLLER_PLLC4_MISC1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 766) #define TEGRA186_CLK_PLLC4_OUT_MUX 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 767) /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when DFLLDISP_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 768) #define TEGRA186_CLK_DFLLDISP_DIV 284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 769) /** @brief output of divider NVDISPLAY_DISP_CLK_DIVISOR in CLK_RST_CONTROLLER_CLK_SOURCE_NVDISPLAY_DISP when PLLDISPHUB_DIV is selected in NVDISPLAY_DISP_CLK_SRC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 770) #define TEGRA186_CLK_PLLDISPHUB_DIV 285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 771) /** fixed /8 divider which is used as the input for TEGRA186_CLK_SOR_SAFE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 772) #define TEGRA186_CLK_PLLP_DIV8 286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 773) /** @brief output of divider CLK_RST_CONTROLLER_BPMP_NIC_RATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 774) #define TEGRA186_CLK_BPMP_NIC 287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 775) /** @brief output of the divider CLK_RST_CONTROLLER_PLLA1_OUT1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 776) #define TEGRA186_CLK_PLL_A_OUT1 288
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 777) /** @deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 778) #define TEGRA186_CLK_GPC2CLK 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 779) /** A fake clock which must be enabled during KFUSE read operations to ensure adequate VDD_CORE voltage. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 780) #define TEGRA186_CLK_KFUSE 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 781) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 782) * @brief controls the PLLE hardware sequencer.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 783) * @details This clock only has enable and disable methods. When the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 784) * PLLE hw sequencer is enabled, PLLE, will be enabled or disabled by
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 785) * hw based on the control signals from the PCIe, SATA and XUSB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 786) * clocks. When the PLLE hw sequencer is disabled, the state of PLLE
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 787) * is controlled by sw using clk_enable/clk_disable on
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 788) * TEGRA186_CLK_PLLE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 789) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 790) #define TEGRA186_CLK_PLLE_PWRSEQ 294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 791) /** fixed 60MHz clock divided down from, TEGRA186_CLK_PLL_U */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 792) #define TEGRA186_CLK_PLLREFE_REF 295
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 793) /** @brief output of mux controlled by SOR0_CLK_SEL0 and SOR0_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 794) #define TEGRA186_CLK_SOR0_OUT 296
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 795) /** @brief output of mux controlled by SOR1_CLK_SEL0 and SOR1_CLK_SEL1 in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 796) #define TEGRA186_CLK_SOR1_OUT 297
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 797) /** @brief fixed /5 divider. Output frequency of this clock is TEGRA186_CLK_PLLREFE_OUT1/5. Used as input for TEGRA186_CLK_EQOS_AXI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 798) #define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 799) /** @brief controls the UTMIP_PLL (aka PLLU) hardware sqeuencer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 800) #define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 801) /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL0_MGMT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 802) #define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 803) /** @brief output of the divider CLK_RST_CONTROLLER_CLK_SOURCE_PEX_USB_PAD_PLL1_MGMT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 804) #define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 805) /** @brief controls the UPHY_PLL0 hardware sqeuencer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 806) #define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 807) /** @brief controls the UPHY_PLL1 hardware sqeuencer */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 808) #define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 809) /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC so the bypass output even be used when the PLL is disabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 810) #define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 811) /** @brief output of the mux controlled by PLLREFE_SEL_CLKIN_PEX in CLK_RST_CONTROLLER_PLLREFE_MISC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 812) #define TEGRA186_CLK_PLLREFE_PEX 307
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 813) /** @brief control for PLLREFE_IDDQ in CLK_RST_CONTROLLER_PLLREFE_MISC to turn on the PLL when enabled */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 814) #define TEGRA186_CLK_PLLREFE_IDDQ 308
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 815) /** @brief output of the divider QSPI_CLK_DIV2_SEL in CLK_RST_CONTROLLER_CLK_SOURCE_QSPI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 816) #define TEGRA186_CLK_QSPI_OUT 309
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 817) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 818) * @brief GPC2CLK-div-2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 819) * @details fixed /2 divider. Output frequency is
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 820) * TEGRA186_CLK_GPC2CLK/2. The frequency of this clock is the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 821) * frequency at which the GPU graphics engine runs. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 822) #define TEGRA186_CLK_GPCCLK 310
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 823) /** @brief output of divider CLK_RST_CONTROLLER_AON_NIC_RATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 824) #define TEGRA186_CLK_AON_NIC 450
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 825) /** @brief output of divider CLK_RST_CONTROLLER_SCE_NIC_RATE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 826) #define TEGRA186_CLK_SCE_NIC 451
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 827) /** Fixed 100MHz PLL for PCIe, SATA and superspeed USB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 828) #define TEGRA186_CLK_PLLE 512
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 829) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 830) #define TEGRA186_CLK_PLLC 513
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 831) /** Fixed 408MHz PLL for use by peripheral clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 832) #define TEGRA186_CLK_PLLP 516
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 833) /** @deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 834) #define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 835) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD_BASE for use by DSI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 836) #define TEGRA186_CLK_PLLD 518
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 837) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD2_BASE for use by HDMI or DP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 838) #define TEGRA186_CLK_PLLD2 519
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 839) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 840) * @brief PLL controlled by CLK_RST_CONTROLLER_PLLREFE_BASE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 841) * @details Note that this clock only controls the VCO output, before
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 842) * the post-divider. See TEGRA186_CLK_PLLREFE_OUT1 for more
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 843) * information.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 844) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 845) #define TEGRA186_CLK_PLLREFE_VCO 520
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 846) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC2_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 847) #define TEGRA186_CLK_PLLC2 521
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 848) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC3_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 849) #define TEGRA186_CLK_PLLC3 522
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 850) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDP_BASE for use as the DP link clock */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 851) #define TEGRA186_CLK_PLLDP 523
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 852) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLC4_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 853) #define TEGRA186_CLK_PLLC4_VCO 524
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 854) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLA1_BASE for use by audio clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 855) #define TEGRA186_CLK_PLLA1 525
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 856) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLNVCSI_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 857) #define TEGRA186_CLK_PLLNVCSI 526
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 858) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLDISPHUB_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 859) #define TEGRA186_CLK_PLLDISPHUB 527
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 860) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLD3_BASE for use by HDMI or DP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 861) #define TEGRA186_CLK_PLLD3 528
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 862) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLBPMPCAM_BASE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 863) #define TEGRA186_CLK_PLLBPMPCAM 531
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 864) /** @brief PLL controlled by CLK_RST_CONTROLLER_PLLAON_BASE for use by IP blocks in the AON domain */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 865) #define TEGRA186_CLK_PLLAON 532
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 866) /** Fixed frequency 960MHz PLL for USB and EAVB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 867) #define TEGRA186_CLK_PLLU 533
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 868) /** fixed /2 divider. Output frequency is TEGRA186_CLK_PLLC4_VCO/2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 869) #define TEGRA186_CLK_PLLC4_VCO_DIV2 535
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 870) /** @brief NAFLL clock source for AXI_CBB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 871) #define TEGRA186_CLK_NAFLL_AXI_CBB 564
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 872) /** @brief NAFLL clock source for BPMP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 873) #define TEGRA186_CLK_NAFLL_BPMP 565
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 874) /** @brief NAFLL clock source for ISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 875) #define TEGRA186_CLK_NAFLL_ISP 566
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 876) /** @brief NAFLL clock source for NVDEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 877) #define TEGRA186_CLK_NAFLL_NVDEC 567
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 878) /** @brief NAFLL clock source for NVENC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 879) #define TEGRA186_CLK_NAFLL_NVENC 568
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 880) /** @brief NAFLL clock source for NVJPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 881) #define TEGRA186_CLK_NAFLL_NVJPG 569
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 882) /** @brief NAFLL clock source for SCE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 883) #define TEGRA186_CLK_NAFLL_SCE 570
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 884) /** @brief NAFLL clock source for SE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 885) #define TEGRA186_CLK_NAFLL_SE 571
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 886) /** @brief NAFLL clock source for TSEC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 887) #define TEGRA186_CLK_NAFLL_TSEC 572
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 888) /** @brief NAFLL clock source for TSECB */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 889) #define TEGRA186_CLK_NAFLL_TSECB 573
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 890) /** @brief NAFLL clock source for VI */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 891) #define TEGRA186_CLK_NAFLL_VI 574
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 892) /** @brief NAFLL clock source for VIC */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 893) #define TEGRA186_CLK_NAFLL_VIC 575
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 894) /** @brief NAFLL clock source for DISP */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 895) #define TEGRA186_CLK_NAFLL_DISP 576
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 896) /** @brief NAFLL clock source for GPU */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 897) #define TEGRA186_CLK_NAFLL_GPU 577
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 898) /** @brief NAFLL clock source for M-CPU cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 899) #define TEGRA186_CLK_NAFLL_MCPU 578
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 900) /** @brief NAFLL clock source for B-CPU cluster */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 901) #define TEGRA186_CLK_NAFLL_BCPU 579
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 902) /** @brief input from Tegra's CLK_32K_IN pad */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 903) #define TEGRA186_CLK_CLK_32K 608
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 904) /** @brief output of divider CLK_RST_CONTROLLER_CLK_M_DIVIDE */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 905) #define TEGRA186_CLK_CLK_M 609
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 906) /** @brief output of divider PLL_REF_DIV in CLK_RST_CONTROLLER_OSC_CTRL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 907) #define TEGRA186_CLK_PLL_REF 610
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 908) /** @brief input from Tegra's XTAL_IN */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 909) #define TEGRA186_CLK_OSC 612
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 910) /** @brief clock recovered from EAVB input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 911) #define TEGRA186_CLK_EQOS_RX_INPUT 613
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 912) /** @brief clock recovered from DTV input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 913) #define TEGRA186_CLK_DTV_INPUT 614
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 914) /** @brief SOR0 brick output which feeds into SOR0_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR0*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 915) #define TEGRA186_CLK_SOR0_PAD_CLKOUT 615
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 916) /** @brief SOR1 brick output which feeds into SOR1_CLK_SEL mux in CLK_RST_CONTROLLER_CLK_SOURCE_SOR1*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 917) #define TEGRA186_CLK_SOR1_PAD_CLKOUT 616
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 918) /** @brief clock recovered from I2S1 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 919) #define TEGRA186_CLK_I2S1_SYNC_INPUT 617
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 920) /** @brief clock recovered from I2S2 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 921) #define TEGRA186_CLK_I2S2_SYNC_INPUT 618
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 922) /** @brief clock recovered from I2S3 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 923) #define TEGRA186_CLK_I2S3_SYNC_INPUT 619
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 924) /** @brief clock recovered from I2S4 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 925) #define TEGRA186_CLK_I2S4_SYNC_INPUT 620
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 926) /** @brief clock recovered from I2S5 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 927) #define TEGRA186_CLK_I2S5_SYNC_INPUT 621
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 928) /** @brief clock recovered from I2S6 input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 929) #define TEGRA186_CLK_I2S6_SYNC_INPUT 622
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 930) /** @brief clock recovered from SPDIFIN input */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 931) #define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 932)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 933) /**
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 934) * @brief subject to change
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 935) * @details maximum clock identifier value plus one.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 936) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 937) #define TEGRA186_CLK_CLK_MAX 624
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 938)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 939) /** @} */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 940)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 941) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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