Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * This header provides constants for binding nvidia,tegra124-car or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * nvidia,tegra132-car.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * The first 192 clocks are numbered to match the bits in the CAR's CLK_OUT_ENB
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * registers. These IDs often match those in the CAR's RST_DEVICES registers,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  * but not in all cases. Some bits in CLK_OUT_ENB affect multiple clocks. In
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  * this case, those clocks are assigned IDs above 185 in order to highlight
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  * this issue. Implementations that interpret these clock IDs as bit values
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  * within the CLK_OUT_ENB or RST_DEVICES registers should be careful to
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  * explicitly handle these special cases.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  * The balance of the clocks controlled by the CAR are assigned IDs of 185 and
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  * above.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #ifndef _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) /* 0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) /* 1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) /* 2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TEGRA124_CLK_ISPB 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TEGRA124_CLK_RTC 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TEGRA124_CLK_TIMER 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TEGRA124_CLK_UARTA 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) /* 7 (register bit affects uartb and vfir) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) /* 8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define TEGRA124_CLK_SDMMC2 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) /* 10 (register bit affects spdif_in and spdif_out) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define TEGRA124_CLK_I2S1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define TEGRA124_CLK_I2C1 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) /* 13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define TEGRA124_CLK_SDMMC1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define TEGRA124_CLK_SDMMC4 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) /* 16 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define TEGRA124_CLK_PWM 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define TEGRA124_CLK_I2S2 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) /* 20 (register bit affects vi and vi_sensor) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) /* 21 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define TEGRA124_CLK_USBD 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define TEGRA124_CLK_ISP 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) /* 26 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) /* 25 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TEGRA124_CLK_DISP2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TEGRA124_CLK_DISP1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TEGRA124_CLK_HOST1X 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TEGRA124_CLK_VCP 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define TEGRA124_CLK_I2S0 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) /* 31 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define TEGRA124_CLK_MC 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) /* 33 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define TEGRA124_CLK_APBDMA 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) /* 35 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define TEGRA124_CLK_KBC 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) /* 37 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) /* 38 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) /* 39 (register bit affects fuse and fuse_burn) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define TEGRA124_CLK_KFUSE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define TEGRA124_CLK_SBC1 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define TEGRA124_CLK_NOR 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) /* 43 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define TEGRA124_CLK_SBC2 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) /* 45 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define TEGRA124_CLK_SBC3 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define TEGRA124_CLK_I2C5 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define TEGRA124_CLK_DSIA 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) /* 49 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define TEGRA124_CLK_MIPI 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define TEGRA124_CLK_HDMI 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define TEGRA124_CLK_CSI 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) /* 53 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define TEGRA124_CLK_I2C2 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define TEGRA124_CLK_UARTC 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define TEGRA124_CLK_MIPI_CAL 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define TEGRA124_CLK_EMC 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define TEGRA124_CLK_USB2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define TEGRA124_CLK_USB3 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) /* 60 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define TEGRA124_CLK_VDE 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define TEGRA124_CLK_BSEA 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define TEGRA124_CLK_BSEV 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) /* 64 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define TEGRA124_CLK_UARTD 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) /* 66 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define TEGRA124_CLK_I2C3 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define TEGRA124_CLK_SBC4 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define TEGRA124_CLK_SDMMC3 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define TEGRA124_CLK_PCIE 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define TEGRA124_CLK_OWR 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define TEGRA124_CLK_AFI 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define TEGRA124_CLK_CSITE 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) /* 74 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) /* 75 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define TEGRA124_CLK_LA 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define TEGRA124_CLK_TRACE 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TEGRA124_CLK_SOC_THERM 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TEGRA124_CLK_DTV 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) /* 80 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define TEGRA124_CLK_I2CSLOW 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define TEGRA124_CLK_DSIB 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TEGRA124_CLK_TSEC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* 84 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* 85 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) /* 86 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) /* 87 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) /* 88 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define TEGRA124_CLK_XUSB_HOST 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) /* 90 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define TEGRA124_CLK_MSENC 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define TEGRA124_CLK_CSUS 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) /* 93 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* 94 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) /* 95 (bit affects xusb_dev and xusb_dev_src) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) /* 96 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) /* 97 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) /* 98 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define TEGRA124_CLK_MSELECT 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define TEGRA124_CLK_TSENSOR 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define TEGRA124_CLK_I2S3 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define TEGRA124_CLK_I2S4 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TEGRA124_CLK_I2C4 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define TEGRA124_CLK_SBC5 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define TEGRA124_CLK_SBC6 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define TEGRA124_CLK_D_AUDIO 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define TEGRA124_CLK_APBIF 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define TEGRA124_CLK_DAM0 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define TEGRA124_CLK_DAM1 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define TEGRA124_CLK_DAM2 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define TEGRA124_CLK_HDA2CODEC_2X 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) /* 112 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define TEGRA124_CLK_AUDIO0_2X 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define TEGRA124_CLK_AUDIO1_2X 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define TEGRA124_CLK_AUDIO2_2X 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define TEGRA124_CLK_AUDIO3_2X 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define TEGRA124_CLK_AUDIO4_2X 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define TEGRA124_CLK_SPDIF_2X 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define TEGRA124_CLK_ACTMON 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define TEGRA124_CLK_EXTERN1 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define TEGRA124_CLK_EXTERN2 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define TEGRA124_CLK_EXTERN3 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define TEGRA124_CLK_SATA_OOB 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define TEGRA124_CLK_SATA 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define TEGRA124_CLK_HDA 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) /* 126 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define TEGRA124_CLK_SE 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define TEGRA124_CLK_HDA2HDMI 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define TEGRA124_CLK_SATA_COLD 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) /* 130 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) /* 131 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) /* 132 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) /* 133 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) /* 134 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) /* 135 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define TEGRA124_CLK_CEC 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) /* 137 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* 138 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) /* 139 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) /* 140 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) /* 141 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) /* 142 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) /* 143 (bit affects xusb_falcon_src, xusb_fs_src, */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /*      xusb_host_src and xusb_ss_src) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define TEGRA124_CLK_CILAB 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define TEGRA124_CLK_CILCD 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define TEGRA124_CLK_CILE 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define TEGRA124_CLK_DSIALP 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define TEGRA124_CLK_DSIBLP 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define TEGRA124_CLK_ENTROPY 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define TEGRA124_CLK_DDS 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) /* 151 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define TEGRA124_CLK_DP2 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define TEGRA124_CLK_AMX 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define TEGRA124_CLK_ADX 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) /* 155 (bit affects dfll_ref and dfll_soc) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define TEGRA124_CLK_XUSB_SS 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* 157 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) /* 158 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) /* 159 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) /* 160 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) /* 161 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* 162 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) /* 163 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) /* 164 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) /* 165 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define TEGRA124_CLK_I2C6 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) /* 167 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) /* 168 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) /* 169 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) /* 170 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define TEGRA124_CLK_VIM2_CLK 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) /* 172 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) /* 173 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) /* 174 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) /* 175 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define TEGRA124_CLK_HDMI_AUDIO 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define TEGRA124_CLK_CLK72MHZ 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define TEGRA124_CLK_VIC03 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* 179 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define TEGRA124_CLK_ADX1 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define TEGRA124_CLK_DPAUX 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TEGRA124_CLK_SOR0 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) /* 183 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define TEGRA124_CLK_GPU 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define TEGRA124_CLK_AMX1 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) /* 186 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) /* 187 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) /* 188 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) /* 189 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) /* 190 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* 191 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TEGRA124_CLK_UARTB 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TEGRA124_CLK_VFIR 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TEGRA124_CLK_SPDIF_IN 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TEGRA124_CLK_SPDIF_OUT 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TEGRA124_CLK_VI 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TEGRA124_CLK_VI_SENSOR 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TEGRA124_CLK_FUSE 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TEGRA124_CLK_FUSE_BURN 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define TEGRA124_CLK_CLK_32K 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define TEGRA124_CLK_CLK_M 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define TEGRA124_CLK_CLK_M_DIV2 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define TEGRA124_CLK_CLK_M_DIV4 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define TEGRA124_CLK_OSC_DIV2 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define TEGRA124_CLK_OSC_DIV4 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define TEGRA124_CLK_PLL_REF 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define TEGRA124_CLK_PLL_C 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define TEGRA124_CLK_PLL_C_OUT1 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define TEGRA124_CLK_PLL_C2 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define TEGRA124_CLK_PLL_C3 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define TEGRA124_CLK_PLL_M 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define TEGRA124_CLK_PLL_M_OUT1 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define TEGRA124_CLK_PLL_P 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define TEGRA124_CLK_PLL_P_OUT1 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define TEGRA124_CLK_PLL_P_OUT2 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define TEGRA124_CLK_PLL_P_OUT3 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define TEGRA124_CLK_PLL_P_OUT4 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define TEGRA124_CLK_PLL_A 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define TEGRA124_CLK_PLL_A_OUT0 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define TEGRA124_CLK_PLL_D 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define TEGRA124_CLK_PLL_D_OUT0 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define TEGRA124_CLK_PLL_D2 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define TEGRA124_CLK_PLL_D2_OUT0 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define TEGRA124_CLK_PLL_U 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define TEGRA124_CLK_PLL_U_480M 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define TEGRA124_CLK_PLL_U_60M 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define TEGRA124_CLK_PLL_U_48M 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define TEGRA124_CLK_PLL_U_12M 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) /* 227 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) /* 228 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define TEGRA124_CLK_PLL_RE_VCO 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define TEGRA124_CLK_PLL_RE_OUT 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define TEGRA124_CLK_PLL_E 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define TEGRA124_CLK_SPDIF_IN_SYNC 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define TEGRA124_CLK_I2S0_SYNC 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define TEGRA124_CLK_I2S1_SYNC 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define TEGRA124_CLK_I2S2_SYNC 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define TEGRA124_CLK_I2S3_SYNC 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define TEGRA124_CLK_I2S4_SYNC 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define TEGRA124_CLK_VIMCLK_SYNC 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define TEGRA124_CLK_AUDIO0 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define TEGRA124_CLK_AUDIO1 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define TEGRA124_CLK_AUDIO2 241
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define TEGRA124_CLK_AUDIO3 242
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define TEGRA124_CLK_AUDIO4 243
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define TEGRA124_CLK_SPDIF 244
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) /* 245 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) /* 246 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) /* 247 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) /* 248 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define TEGRA124_CLK_OSC 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) /* 250 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) /* 251 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define TEGRA124_CLK_XUSB_HOST_SRC 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define TEGRA124_CLK_XUSB_FALCON_SRC 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define TEGRA124_CLK_XUSB_FS_SRC 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define TEGRA124_CLK_XUSB_SS_SRC 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define TEGRA124_CLK_XUSB_DEV_SRC 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define TEGRA124_CLK_XUSB_DEV 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define TEGRA124_CLK_XUSB_HS_SRC 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define TEGRA124_CLK_SCLK 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define TEGRA124_CLK_HCLK 260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define TEGRA124_CLK_PCLK 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) /* 262 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) /* 263 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define TEGRA124_CLK_DFLL_REF 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define TEGRA124_CLK_DFLL_SOC 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define TEGRA124_CLK_VI_SENSOR2 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define TEGRA124_CLK_PLL_P_OUT5 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define TEGRA124_CLK_CML0 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define TEGRA124_CLK_CML1 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define TEGRA124_CLK_PLL_C4 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define TEGRA124_CLK_PLL_DP 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define TEGRA124_CLK_PLL_E_MUX 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define TEGRA124_CLK_PLL_D_DSI_OUT 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) /* 274 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) /* 275 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) /* 276 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* 277 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) /* 278 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) /* 279 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) /* 280 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) /* 281 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) /* 282 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) /* 283 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) /* 284 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) /* 285 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) /* 286 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) /* 287 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) /* 288 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) /* 289 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) /* 290 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) /* 291 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) /* 292 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) /* 293 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) /* 294 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) /* 295 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) /* 296 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) /* 297 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) /* 298 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) /* 299 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define TEGRA124_CLK_AUDIO0_MUX 300
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define TEGRA124_CLK_AUDIO1_MUX 301
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define TEGRA124_CLK_AUDIO2_MUX 302
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define TEGRA124_CLK_AUDIO3_MUX 303
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define TEGRA124_CLK_AUDIO4_MUX 304
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define TEGRA124_CLK_SPDIF_MUX 305
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) /* 306 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) /* 307 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) /* 308 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) /* 309 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) /* 310 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define TEGRA124_CLK_SOR0_LVDS 311 /* deprecated */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define TEGRA124_CLK_SOR0_OUT 311
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define TEGRA124_CLK_XUSB_SS_DIV2 312
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define TEGRA124_CLK_PLL_M_UD 313
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define TEGRA124_CLK_PLL_C_UD 314
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #endif	/* _DT_BINDINGS_CLOCK_TEGRA124_CAR_COMMON_H */