Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2018 Icenowy Zheng <icenowy@aosc.xyz>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #ifndef _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #define _DT_BINDINGS_CLK_SUNIV_F1C100S_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define CLK_CPU			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_BUS_DMA		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_BUS_MMC0		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_BUS_MMC1		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_BUS_DRAM		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_BUS_SPI0		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_BUS_SPI1		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_BUS_OTG		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_BUS_VE		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_BUS_LCD		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_BUS_DEINTERLACE	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_BUS_CSI		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_BUS_TVD		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_BUS_TVE		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_BUS_DE_BE		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_BUS_DE_FE		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_BUS_CODEC		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_BUS_SPDIF		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_BUS_IR		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_BUS_RSB		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_BUS_I2S0		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_BUS_I2C0		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_BUS_I2C1		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_BUS_I2C2		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_BUS_PIO		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_BUS_UART0		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_BUS_UART1		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_BUS_UART2		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_MMC0		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_MMC0_SAMPLE		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_MMC0_OUTPUT		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_MMC1		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_MMC1_SAMPLE		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_MMC1_OUTPUT		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_I2S			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_SPDIF		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_USB_PHY0		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_DRAM_VE		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_DRAM_CSI		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_DRAM_DEINTERLACE	52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_DRAM_TVD		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_DRAM_DE_FE		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_DRAM_DE_BE		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_DE_BE		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_DE_FE		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_TCON		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_DEINTERLACE		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_TVE2_CLK		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_TVE1_CLK		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_TVD			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_CSI			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_VE			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_CODEC		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_AVS			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif