Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2)  * Copyright (C) 2016 Chen-Yu Tsai <wens@csie.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * This file is dual-licensed: you can use it either under the terms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * of the GPL or the X11 license, at your option. Note that this dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  * licensing only applies to this file, and not this project as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7)  * whole.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9)  *  a) This file is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10)  *     modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11)  *     published by the Free Software Foundation; either version 2 of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12)  *     License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14)  *     This file is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15)  *     but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16)  *     MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17)  *     GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19)  * Or, alternatively,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21)  *  b) Permission is hereby granted, free of charge, to any person
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22)  *     obtaining a copy of this software and associated documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23)  *     files (the "Software"), to deal in the Software without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24)  *     restriction, including without limitation the rights to use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25)  *     copy, modify, merge, publish, distribute, sublicense, and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26)  *     sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27)  *     Software is furnished to do so, subject to the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28)  *     conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30)  *     The above copyright notice and this permission notice shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31)  *     included in all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33)  *     THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34)  *     EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35)  *     OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36)  *     NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37)  *     HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38)  *     WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39)  *     FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40)  *     OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #ifndef _DT_BINDINGS_CLK_SUN6I_A31_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define _DT_BINDINGS_CLK_SUN6I_A31_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_PLL_VIDEO0_2X	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_PLL_PERIPH		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_PLL_VIDEO1_2X	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CLK_PLL_MIPI		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLK_CPU			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define CLK_AHB1_MIPIDSI	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CLK_AHB1_SS		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CLK_AHB1_DMA		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_AHB1_MMC0		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_AHB1_MMC1		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_AHB1_MMC2		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_AHB1_MMC3		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_AHB1_NAND1		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_AHB1_NAND0		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_AHB1_SDRAM		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define CLK_AHB1_EMAC		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLK_AHB1_TS		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_AHB1_HSTIMER	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLK_AHB1_SPI0		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLK_AHB1_SPI1		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLK_AHB1_SPI2		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define CLK_AHB1_SPI3		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLK_AHB1_OTG		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CLK_AHB1_EHCI0		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CLK_AHB1_EHCI1		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLK_AHB1_OHCI0		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLK_AHB1_OHCI1		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLK_AHB1_OHCI2		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLK_AHB1_VE		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_AHB1_LCD0		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CLK_AHB1_LCD1		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CLK_AHB1_CSI		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CLK_AHB1_HDMI		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLK_AHB1_BE0		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CLK_AHB1_BE1		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CLK_AHB1_FE0		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CLK_AHB1_FE1		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLK_AHB1_MP		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CLK_AHB1_GPU		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLK_AHB1_DEU0		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLK_AHB1_DEU1		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLK_AHB1_DRC0		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLK_AHB1_DRC1		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK_APB1_CODEC		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CLK_APB1_SPDIF		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CLK_APB1_DIGITAL_MIC	63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CLK_APB1_PIO		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CLK_APB1_DAUDIO0	65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_APB1_DAUDIO1	66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_APB2_I2C0		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_APB2_I2C1		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_APB2_I2C2		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_APB2_I2C3		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_APB2_UART0		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_APB2_UART1		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_APB2_UART2		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_APB2_UART3		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_APB2_UART4		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_APB2_UART5		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_NAND0		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_NAND1		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_MMC0		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_MMC0_SAMPLE		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_MMC0_OUTPUT		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_MMC1		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_MMC1_SAMPLE		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_MMC1_OUTPUT		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_MMC2		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_MMC2_SAMPLE		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_MMC2_OUTPUT		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_MMC3		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_MMC3_SAMPLE		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_MMC3_OUTPUT		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_TS			91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_SS			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_SPI0		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_SPI1		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_SPI2		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_SPI3		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_DAUDIO0		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_DAUDIO1		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_SPDIF		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_USB_PHY0		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_USB_PHY1		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_USB_PHY2		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_USB_OHCI0		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_USB_OHCI1		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_USB_OHCI2		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_DRAM_VE		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_DRAM_CSI_ISP	111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_DRAM_TS		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_DRAM_DRC0		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_DRAM_DRC1		114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_DRAM_DEU0		115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_DRAM_DEU1		116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_DRAM_FE0		117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_DRAM_FE1		118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_DRAM_BE0		119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_DRAM_BE1		120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_DRAM_MP		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_BE0			122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_BE1			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_FE0			124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_FE1			125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_MP			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_LCD0_CH0		127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_LCD1_CH0		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_LCD0_CH1		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_LCD1_CH1		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_CSI0_SCLK		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_CSI0_MCLK		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_CSI1_MCLK		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_VE			134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_CODEC		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_AVS			136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_DIGITAL_MIC		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_HDMI		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_HDMI_DDC		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_PS			140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_MIPI_DSI		143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_MIPI_DSI_DPHY	144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_MIPI_CSI_DPHY	145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_IEP_DRC0		146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_IEP_DRC1		147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_IEP_DEU0		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_IEP_DEU1		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_GPU_CORE		150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_GPU_MEMORY		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_GPU_HYD		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_ATS			153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_TRACE		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_OUT_A		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_OUT_B		156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_OUT_C		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #endif /* _DT_BINDINGS_CLK_SUN6I_A31_H_ */