^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright 2016 Maxime Ripard
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Maxime Ripard <maxime.ripard@free-electrons.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DT_BINDINGS_CLK_SUN5I_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DT_BINDINGS_CLK_SUN5I_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLK_HOSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_PLL_VIDEO0_2X 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_PLL_VIDEO1_2X 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_CPU 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_AHB_OTG 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_AHB_EHCI 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_AHB_OHCI 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_AHB_SS 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_AHB_DMA 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_AHB_BIST 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_AHB_MMC0 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_AHB_MMC1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_AHB_MMC2 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_AHB_NAND 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_AHB_SDRAM 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_AHB_EMAC 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_AHB_TS 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_AHB_SPI0 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_AHB_SPI1 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_AHB_SPI2 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_AHB_GPS 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_AHB_HSTIMER 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_AHB_VE 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_AHB_TVE 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_AHB_LCD 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_AHB_CSI 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_AHB_HDMI 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_AHB_DE_BE 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_AHB_DE_FE 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_AHB_IEP 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_AHB_GPU 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_APB0_CODEC 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_APB0_SPDIF 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_APB0_I2S 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_APB0_PIO 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_APB0_IR 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_APB0_KEYPAD 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_APB1_I2C0 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_APB1_I2C1 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_APB1_I2C2 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_APB1_UART0 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_APB1_UART1 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_APB1_UART2 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_APB1_UART3 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_NAND 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_MMC0 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_MMC1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_MMC2 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_TS 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_SS 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_SPI0 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_SPI1 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_SPI2 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_IR 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_I2S 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_SPDIF 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_KEYPAD 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_USB_OHCI 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_USB_PHY0 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_USB_PHY1 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_GPS 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_DRAM_VE 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_DRAM_CSI 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_DRAM_TS 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_DRAM_TVE 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_DRAM_DE_FE 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_DRAM_DE_BE 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_DRAM_ACE 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLK_DRAM_IEP 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLK_DE_BE 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_DE_FE 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_TCON_CH0 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_TCON_CH1 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_CSI 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLK_VE 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_CODEC 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_AVS 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_HDMI 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_GPU 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLK_MBUS 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_IEP 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #endif /* _DT_BINDINGS_CLK_SUN5I_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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