^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) // SPDX-License-Identifier: (GPL-2.0+ or MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2017 Icenowy Zheng <icenowy@aosc.io>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLK_SUN50I_H6_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLK_SUN50I_H6_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CLK_PLL_PERIPH0 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLK_CPUX 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_APB1 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_DE 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_BUS_DE 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_DEINTERLACE 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_BUS_DEINTERLACE 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_GPU 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_BUS_GPU 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_CE 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_BUS_CE 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_VE 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_BUS_VE 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_EMCE 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_BUS_EMCE 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_VP9 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_BUS_VP9 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_BUS_DMA 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_BUS_MSGBOX 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_BUS_SPINLOCK 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_BUS_HSTIMER 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_AVS 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_BUS_DBG 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_BUS_PSI 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_BUS_PWM 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_BUS_IOMMU 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_MBUS_DMA 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_MBUS_VE 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_MBUS_CE 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_MBUS_TS 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_MBUS_NAND 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_MBUS_CSI 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_MBUS_DEINTERLACE 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_NAND0 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_NAND1 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_BUS_NAND 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_MMC0 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_MMC1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_MMC2 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_BUS_MMC0 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_BUS_MMC1 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_BUS_MMC2 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_BUS_UART0 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_BUS_UART1 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_BUS_UART2 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_BUS_UART3 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_BUS_I2C0 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_BUS_I2C1 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_BUS_I2C2 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_BUS_I2C3 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_BUS_SCR0 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_BUS_SCR1 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_SPI0 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_SPI1 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_BUS_SPI0 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_BUS_SPI1 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_BUS_EMAC 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_TS 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_BUS_TS 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_IR_TX 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_BUS_IR_TX 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_BUS_THS 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_I2S3 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_I2S0 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_I2S1 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_I2S2 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_BUS_I2S0 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_BUS_I2S1 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLK_BUS_I2S2 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLK_BUS_I2S3 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_SPDIF 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_BUS_SPDIF 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLK_DMIC 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_BUS_DMIC 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_AUDIO_HUB 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLK_BUS_AUDIO_HUB 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_USB_OHCI0 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_USB_PHY0 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_USB_PHY1 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_USB_OHCI3 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define CLK_USB_PHY3 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define CLK_USB_HSIC_12M 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_USB_HSIC 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_BUS_OHCI0 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_BUS_OHCI3 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK_BUS_EHCI0 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_BUS_XHCI 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_BUS_EHCI3 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_BUS_OTG 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_PCIE_REF_100M 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_PCIE_REF 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_PCIE_REF_OUT 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_PCIE_MAXI 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_PCIE_AUX 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_BUS_PCIE 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_HDMI 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_HDMI_SLOW 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_HDMI_CEC 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_BUS_HDMI 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_BUS_TCON_TOP 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_TCON_LCD0 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_BUS_TCON_LCD0 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_TCON_TV0 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_BUS_TCON_TV0 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_CSI_CCI 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_CSI_TOP 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_CSI_MCLK 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_BUS_CSI 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_HDCP 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_BUS_HDCP 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #endif /* _DT_BINDINGS_CLK_SUN50I_H6_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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