^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2020 Yangtao Li <frank@allwinnertech.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #ifndef _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define CLK_R_APB1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CLK_R_APB1_TIMER 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define CLK_R_APB1_TWD 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define CLK_R_APB1_PWM 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_R_APB1_BUS_PWM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_R_APB1_PPU 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_R_APB2_UART 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_R_APB2_I2C0 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_R_APB2_I2C1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_R_APB1_IR 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_R_APB1_BUS_IR 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_R_AHB_BUS_RTC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #endif /* _DT_BINDINGS_CLK_SUN50I_A100_R_CCU_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags