^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) * Copyright (C) 2017 Priit Laes <plaes@plaes.org>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * This file is dual-licensed: you can use it either under the terms
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * of the GPL or the X11 license, at your option. Note that this dual
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * licensing only applies to this file, and not this project as a
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) * whole.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * a) This file is free software; you can redistribute it and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) * modify it under the terms of the GNU General Public License as
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) * published by the Free Software Foundation; either version 2 of the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * License, or (at your option) any later version.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * This file is distributed in the hope that it will be useful,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * but WITHOUT ANY WARRANTY; without even the implied warranty of
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) * GNU General Public License for more details.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) * Or, alternatively,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) * b) Permission is hereby granted, free of charge, to any person
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) * obtaining a copy of this software and associated documentation
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) * files (the "Software"), to deal in the Software without
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) * restriction, including without limitation the rights to use,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) * copy, modify, merge, publish, distribute, sublicense, and/or
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) * sell copies of the Software, and to permit persons to whom the
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) * Software is furnished to do so, subject to the following
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) * conditions:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) * The above copyright notice and this permission notice shall be
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) * included in all copies or substantial portions of the Software.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) * EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) * NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR COPYRIGHT
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) * HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY,
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) * OTHER DEALINGS IN THE SOFTWARE.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #ifndef _DT_BINDINGS_CLK_SUN4I_A10_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define _DT_BINDINGS_CLK_SUN4I_A10_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_HOSC 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_PLL_VIDEO0_2X 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_PLL_VIDEO1_2X 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_CPU 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) /* AHB Gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_AHB_OTG 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_AHB_EHCI0 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_AHB_OHCI0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_AHB_EHCI1 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_AHB_OHCI1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_AHB_SS 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_AHB_DMA 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_AHB_BIST 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_AHB_MMC0 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_AHB_MMC1 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLK_AHB_MMC2 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define CLK_AHB_MMC3 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define CLK_AHB_MS 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define CLK_AHB_NAND 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define CLK_AHB_SDRAM 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define CLK_AHB_ACE 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define CLK_AHB_EMAC 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define CLK_AHB_TS 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define CLK_AHB_SPI0 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define CLK_AHB_SPI1 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define CLK_AHB_SPI2 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define CLK_AHB_SPI3 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CLK_AHB_PATA 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_AHB_SATA 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_AHB_GPS 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_AHB_HSTIMER 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_AHB_VE 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_AHB_TVD 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_AHB_TVE0 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define CLK_AHB_TVE1 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define CLK_AHB_LCD0 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define CLK_AHB_LCD1 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define CLK_AHB_CSI0 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define CLK_AHB_CSI1 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define CLK_AHB_HDMI0 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define CLK_AHB_HDMI1 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define CLK_AHB_DE_BE0 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define CLK_AHB_DE_BE1 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define CLK_AHB_DE_FE0 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define CLK_AHB_DE_FE1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define CLK_AHB_GMAC 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define CLK_AHB_MP 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define CLK_AHB_GPU 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) /* APB0 Gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define CLK_APB0_CODEC 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define CLK_APB0_SPDIF 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define CLK_APB0_I2S0 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define CLK_APB0_AC97 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_APB0_I2S1 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_APB0_PIO 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_APB0_IR0 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_APB0_IR1 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_APB0_I2S2 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_APB0_KEYPAD 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) /* APB1 Gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_APB1_I2C0 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_APB1_I2C1 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_APB1_I2C2 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_APB1_I2C3 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_APB1_CAN 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_APB1_SCR 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_APB1_PS20 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_APB1_PS21 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_APB1_I2C4 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_APB1_UART0 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_APB1_UART1 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_APB1_UART2 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_APB1_UART3 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_APB1_UART4 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_APB1_UART5 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_APB1_UART6 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_APB1_UART7 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) /* IP clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_NAND 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_MS 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_MMC0 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_MMC0_OUTPUT 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_MMC0_SAMPLE 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_MMC1 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_MMC1_OUTPUT 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_MMC1_SAMPLE 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_MMC2 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_MMC2_OUTPUT 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_MMC2_SAMPLE 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_MMC3 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_MMC3_OUTPUT 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_MMC3_SAMPLE 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_TS 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_SS 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_SPI0 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_SPI1 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_SPI2 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_PATA 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_IR0 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_IR1 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_I2S0 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_AC97 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_SPDIF 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_KEYPAD 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_SATA 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_USB_OHCI0 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_USB_OHCI1 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_USB_PHY 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_GPS 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_SPI3 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_I2S1 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_I2S2 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) /* DRAM Gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_DRAM_VE 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_DRAM_CSI0 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_DRAM_CSI1 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_DRAM_TS 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_DRAM_TVD 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_DRAM_TVE0 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_DRAM_TVE1 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_DRAM_OUT 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_DRAM_DE_FE1 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_DRAM_DE_FE0 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_DRAM_DE_BE0 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_DRAM_DE_BE1 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_DRAM_MP 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_DRAM_ACE 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) /* Display Engine Clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_DE_BE0 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_DE_BE1 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_DE_FE0 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_DE_FE1 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_DE_MP 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_TCON0_CH0 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_TCON1_CH0 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_CSI_SCLK 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_TVD_SCLK2 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_TVD 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_TCON0_CH1_SCLK2 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_TCON0_CH1 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_TCON1_CH1_SCLK2 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLK_TCON1_CH1 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLK_CSI0 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_CSI1 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_CODEC 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_VE 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_AVS 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_ACE 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_HDMI 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_GPU 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #endif /* _DT_BINDINGS_CLK_SUN4I_A10_H_ */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags