Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0 or BSD-3-Clause */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (C) STMicroelectronics 2018 - All Rights Reserved
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Gabriel Fernandez <gabriel.fernandez@st.com> for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_STM32MP1_CLKS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_STM32MP1_CLKS_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* OSCILLATOR clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define CK_HSE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CK_CSI		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CK_LSI		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CK_LSE		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CK_HSI		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CK_HSE_DIV2	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) /* Bus clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define TIM2		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define TIM3		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define TIM4		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define TIM5		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define TIM6		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define TIM7		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define TIM12		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define TIM13		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define TIM14		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define LPTIM1		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SPI2		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SPI3		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define USART2		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define USART3		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define UART4		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define UART5		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define UART7		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define UART8		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define I2C1		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define I2C2		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define I2C3		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define I2C5		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SPDIF		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CEC		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define DAC12		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define MDIO		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define TIM1		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define TIM8		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define TIM15		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define TIM16		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define TIM17		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SPI1		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SPI4		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SPI5		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define USART6		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SAI1		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SAI2		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SAI3		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define DFSDM		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define FDCAN		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define LPTIM2		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define LPTIM3		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define LPTIM4		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define LPTIM5		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SAI4		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SYSCFG		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define VREF		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define TMPSENS		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define PMBCTRL		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define HDP		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define LTDC		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define DSI		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define IWDG2		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define USBPHY		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define STGENRO		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SPI6		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define I2C4		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define I2C6		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define USART1		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define RTCAPB		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define TZC1		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define TZPC		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define IWDG1		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define BSEC		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define STGEN		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define DMA1		71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define DMA2		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define DMAMUX		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define ADC12		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define USBO		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define SDMMC3		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define DCMI		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CRYP2		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define HASH2		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define RNG2		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CRC2		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define HSEM		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define IPCC		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define GPIOA		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define GPIOB		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define GPIOC		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define GPIOD		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define GPIOE		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define GPIOF		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define GPIOG		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define GPIOH		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define GPIOI		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define GPIOJ		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define GPIOK		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define GPIOZ		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CRYP1		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define HASH1		97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RNG1		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define BKPSRAM		99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define MDMA		100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define GPU		101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define ETHCK		102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define ETHTX		103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define ETHRX		104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define ETHMAC		105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define FMC		106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define QSPI		107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SDMMC1		108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define SDMMC2		109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CRC1		110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define USBH		111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define ETHSTP		112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define TZC2		113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) /* Kernel clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define SDMMC1_K	118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define SDMMC2_K	119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define SDMMC3_K	120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define FMC_K		121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define QSPI_K		122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define ETHCK_K		123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define RNG1_K		124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define RNG2_K		125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define GPU_K		126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define USBPHY_K	127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define STGEN_K		128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SPDIF_K		129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SPI1_K		130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define SPI2_K		131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define SPI3_K		132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SPI4_K		133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define SPI5_K		134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SPI6_K		135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CEC_K		136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define I2C1_K		137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define I2C2_K		138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define I2C3_K		139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define I2C4_K		140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define I2C5_K		141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define I2C6_K		142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define LPTIM1_K	143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define LPTIM2_K	144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define LPTIM3_K	145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LPTIM4_K	146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define LPTIM5_K	147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define USART1_K	148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define USART2_K	149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define USART3_K	150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define UART4_K		151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define UART5_K		152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define USART6_K	153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define UART7_K		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define UART8_K		155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DFSDM_K		156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define FDCAN_K		157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SAI1_K		158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SAI2_K		159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SAI3_K		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SAI4_K		161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define ADC12_K		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define DSI_K		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define DSI_PX		164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define ADFSDM_K	165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define USBO_K		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define LTDC_PX		167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define DAC12_K		168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ETHPTP_K	169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) /* PLL */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define PLL1		176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PLL2		177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PLL3		178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PLL4		179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) /* ODF */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PLL1_P		180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PLL1_Q		181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define PLL1_R		182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PLL2_P		183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define PLL2_Q		184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define PLL2_R		185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define PLL3_P		186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define PLL3_Q		187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PLL3_R		188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define PLL4_P		189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PLL4_Q		190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define PLL4_R		191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) /* AUX */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define RTC		192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) /* MCLK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CK_PER		193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CK_MPU		194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CK_AXI		195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CK_MCU		196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) /* Time base */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define TIM2_K		197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define TIM3_K		198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define TIM4_K		199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define TIM5_K		200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define TIM6_K		201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define TIM7_K		202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define TIM12_K		203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define TIM13_K		204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define TIM14_K		205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define TIM1_K		206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define TIM8_K		207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define TIM15_K		208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define TIM16_K		209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define TIM17_K		210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) /* MCO clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CK_MCO1		211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CK_MCO2		212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) /* TRACE & DEBUG clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CK_DBG		214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CK_TRACE	215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) /* DDR */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define DDRC1		220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define DDRC1LP		221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define DDRC2		222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define DDRC2LP		223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define DDRPHYC		224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define DDRPHYCLP	225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define DDRCAPB		226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define DDRCAPBLP	227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define AXIDCG		228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define DDRPHYCAPB	229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define DDRPHYCAPBLP	230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define DDRPERFM	231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define STM32MP1_LAST_CLK 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */