^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SYS, CORE AND BUS CLOCKS */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) #define SYS_D1CPRE 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) #define HCLK 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) #define PCLK1 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) #define PCLK2 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) #define PCLK3 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #define PCLK4 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define HSI_DIV 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define HSE_1M 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define I2S_CKIN 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define CK_DSI_PHY 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define HSE_CK 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define LSE_CK 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CSI_KER_DIV122 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define RTC_CK 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CPU_SYSTICK 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) /* OSCILLATOR BANK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define OSC_BANK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define HSI_CK 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define HSI_KER_CK 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CSI_CK 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CSI_KER_CK 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define RC48_CK 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define LSI_CK 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) /* MCLOCK BANK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MCLK_BANK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PER_CK 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define PLLSRC 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SYS_CK 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define TRACEIN_CK 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) /* ODF BANK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define ODF_BANK 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define PLL1_P 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define PLL1_Q 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define PLL1_R 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define PLL2_P 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define PLL2_Q 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PLL2_R 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PLL3_P 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PLL3_Q 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PLL3_R 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* MCO BANK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MCO_BANK 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MCO1 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MCO2 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) /* PERIF BANK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PERIF_BANK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define D1SRAM1_CK 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define ITCM_CK 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define DTCM2_CK 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define DTCM1_CK 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define FLITF_CK 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define JPGDEC_CK 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define DMA2D_CK 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define MDMA_CK 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define USB2ULPI_CK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define USB1ULPI_CK 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define ETH1RX_CK 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define ETH1TX_CK 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define ETH1MAC_CK 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define ART_CK 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DMA2_CK 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DMA1_CK 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define D2SRAM3_CK 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define D2SRAM2_CK 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define D2SRAM1_CK 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define HASH_CK 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define CRYPT_CK 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CAMITF_CK 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define BKPRAM_CK 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define HSEM_CK 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define BDMA_CK 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CRC_CK 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define GPIOK_CK 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define GPIOJ_CK 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define GPIOI_CK 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define GPIOH_CK 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define GPIOG_CK 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define GPIOF_CK 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define GPIOE_CK 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define GPIOD_CK 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define GPIOC_CK 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define GPIOB_CK 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define GPIOA_CK 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define WWDG1_CK 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DAC12_CK 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define WWDG2_CK 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define TIM14_CK 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define TIM13_CK 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define TIM12_CK 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define TIM7_CK 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define TIM6_CK 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define TIM5_CK 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define TIM4_CK 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define TIM3_CK 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define TIM2_CK 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define MDIOS_CK 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define OPAMP_CK 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CRS_CK 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define TIM17_CK 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define TIM16_CK 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define TIM15_CK 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define TIM8_CK 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define TIM1_CK 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define TMPSENS_CK 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define RTCAPB_CK 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define VREF_CK 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define COMP12_CK 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SYSCFG_CK 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) /* KERNEL BANK */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define KERN_BANK 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SDMMC1_CK 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define QUADSPI_CK 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define FMC_CK 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define USB2OTG_CK 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define USB1OTG_CK 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define ADC12_CK 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define SDMMC2_CK 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define RNG_CK 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define ADC3_CK 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define DSI_CK 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define LTDC_CK 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define USART8_CK 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define USART7_CK 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define HDMICEC_CK 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define I2C3_CK 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define I2C2_CK 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define I2C1_CK 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define UART5_CK 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define UART4_CK 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define USART3_CK 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define USART2_CK 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define SPDIFRX_CK 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define SPI3_CK 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define SPI2_CK 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define LPTIM1_CK 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define FDCAN_CK 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define SWP_CK 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HRTIM_CK 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define DFSDM1_CK 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SAI3_CK 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SAI2_CK 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SAI1_CK 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define SPI5_CK 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define SPI4_CK 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define SPI1_CK 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define USART6_CK 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define USART1_CK 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define SAI4B_CK 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define SAI4A_CK 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define LPTIM5_CK 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define LPTIM4_CK 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define LPTIM3_CK 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define LPTIM2_CK 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define I2C4_CK 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define SPI6_CK 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define LPUART1_CK 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define STM32H7_MAX_CLKS 166
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags