Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * stm32fx-clock.h
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Copyright (C) 2016 STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  * Author: Gabriel Fernandez for STMicroelectronics.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)  * List of clocks wich are not derived from system clock (SYSCLOCK)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * The index of these clocks is the secondary index of DT bindings
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * (see Documentatoin/devicetree/bindings/clock/st,stm32-rcc.txt)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * e.g:
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) 	<assigned-clocks = <&rcc 1 CLK_LSE>;
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #ifndef _DT_BINDINGS_CLK_STMFX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define _DT_BINDINGS_CLK_STMFX_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SYSTICK			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FCLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_LSI			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_LSE			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_HSE_RTC		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_RTC			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PLL_VCO_I2S		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define PLL_VCO_SAI		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_LCD			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_I2S			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_SAI1		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_SAI2		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_I2SQ_PDIV		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_SAIQ_PDIV		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_HSI			14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_SYSCLK		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_F469_DSI		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define END_PRIMARY_CLK		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define CLK_HDMI_CEC		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define CLK_SPDIF		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define CLK_USART1		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define CLK_USART2		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define CLK_USART3		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define CLK_UART4		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define CLK_UART5		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define CLK_USART6		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define CLK_UART7		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define CLK_UART8		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define CLK_I2C1		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define CLK_I2C2		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define CLK_I2C3		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define CLK_I2C4		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define CLK_LPTIMER		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define CLK_PLL_SRC		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define CLK_DFSDM1		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define CLK_ADFSDM1		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define CLK_F769_DSI		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define END_PRIMARY_CLK_F7	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #endif