Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides constants clk index STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * STiH418 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_CLK_STIH418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_CLK_STIH418
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "stih410-clks.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* STiH418 introduces new clock outputs compared to STiH410 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* CLOCKGEN C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_PROC_BDISP_0        14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_PROC_BDISP_1        15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_TX_ICN_1            23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_ETH_PHYREF          27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_PP_HEVC             35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_CLUST_HEVC          36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_HWPE_HEVC           37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_FC_HEVC             38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_PROC_MIXER		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_PROC_SC		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_AVSP_HEVC		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* CLOCKGEN D2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #undef CLK_PIX_PIP
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #undef CLK_PIX_GDP1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #undef CLK_PIX_GDP2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #undef CLK_PIX_GDP3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #undef CLK_PIX_GDP4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define CLK_TMDS_HDMI_DIV2	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_VP9			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #endif