Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * This header provides constants clk index STMicroelectronics
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  * STiH410 SoC.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef _DT_BINDINGS_CLK_STIH410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define _DT_BINDINGS_CLK_STIH410
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #include "stih407-clks.h"
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* STiH410 introduces new clock outputs compared to STiH407 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) /* CLOCKGEN C0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define CLK_TX_ICN_HADES	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_RX_ICN_HADES	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_ICN_REG_16		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_PP_HADES		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_CLUST_HADES		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_HWPE_HADES		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_FC_HADES		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) /* CLOCKGEN D0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_PCMR10_MASTER	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_USB2_PHY		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #endif