Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Unisoc SC9863A platform clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  * Copyright (C) 2019, Unisoc Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #ifndef _DT_BINDINGS_CLK_SC9863A_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) #define _DT_BINDINGS_CLK_SC9863A_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define CLK_MPLL0_GATE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define CLK_DPLL0_GATE		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define CLK_LPLL_GATE		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define CLK_GPLL_GATE		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define CLK_DPLL1_GATE		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define CLK_MPLL1_GATE		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define CLK_MPLL2_GATE		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define CLK_ISPPLL_GATE		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define CLK_PMU_APB_NUM		(CLK_ISPPLL_GATE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define CLK_AUDIO_GATE		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define CLK_RPLL		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define CLK_RPLL_390M		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define CLK_RPLL_260M		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define CLK_RPLL_195M		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define CLK_RPLL_26M		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define CLK_ANLG_PHY_G5_NUM	(CLK_RPLL_26M + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define CLK_TWPLL		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define CLK_TWPLL_768M		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define CLK_TWPLL_384M		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CLK_TWPLL_192M		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define CLK_TWPLL_96M		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define CLK_TWPLL_48M		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define CLK_TWPLL_24M		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define CLK_TWPLL_12M		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define CLK_TWPLL_512M		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define CLK_TWPLL_256M		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define CLK_TWPLL_128M		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define CLK_TWPLL_64M		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define CLK_TWPLL_307M2		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define CLK_TWPLL_219M4		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define CLK_TWPLL_170M6		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define CLK_TWPLL_153M6		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define CLK_TWPLL_76M8		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define CLK_TWPLL_51M2		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define CLK_TWPLL_38M4		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define CLK_TWPLL_19M2		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define CLK_LPLL		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define CLK_LPLL_409M6		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define CLK_LPLL_245M76		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define CLK_GPLL		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define CLK_ISPPLL		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define CLK_ISPPLL_468M		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define CLK_ANLG_PHY_G1_NUM	(CLK_ISPPLL_468M + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define CLK_DPLL0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define CLK_DPLL1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define CLK_DPLL0_933M		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define CLK_DPLL0_622M3		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define CLK_DPLL0_400M		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define CLK_DPLL0_266M7		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define CLK_DPLL0_123M1		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define CLK_DPLL0_50M		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define CLK_ANLG_PHY_G7_NUM	(CLK_DPLL0_50M + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define CLK_MPLL0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define CLK_MPLL1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define CLK_MPLL2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define CLK_MPLL2_675M		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define CLK_ANLG_PHY_G4_NUM	(CLK_MPLL2_675M + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define CLK_AP_APB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define CLK_AP_CE		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define CLK_NANDC_ECC		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define CLK_NANDC_26M		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define CLK_EMMC_32K		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define CLK_SDIO0_32K		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define CLK_SDIO1_32K		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_SDIO2_32K		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define CLK_OTG_UTMI		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define CLK_AP_UART0		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define CLK_AP_UART1		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define CLK_AP_UART2		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define CLK_AP_UART3		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define CLK_AP_UART4		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define CLK_AP_I2C0		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define CLK_AP_I2C1		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define CLK_AP_I2C2		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define CLK_AP_I2C3		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define CLK_AP_I2C4		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define CLK_AP_I2C5		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define CLK_AP_I2C6		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define CLK_AP_SPI0		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define CLK_AP_SPI1		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define CLK_AP_SPI2		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define CLK_AP_SPI3		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define CLK_AP_IIS0		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define CLK_AP_IIS1		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_AP_IIS2		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_SIM0		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_SIM0_32K		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_AP_CLK_NUM		(CLK_SIM0_32K + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_13M			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_6M5			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_4M3			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_2M			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_250K		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_RCO_25M		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_RCO_4M		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_RCO_2M		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_EMC			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_AON_APB		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_ADI			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_AUX0		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_AUX1		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_AUX2		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_PROBE		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_PWM0		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_PWM1		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_PWM2		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_AON_THM		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_AUDIF		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_CPU_DAP		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_CPU_TS		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_DJTAG_TCK		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_EMC_REF		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_CSSYS		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_AON_PMU		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_PMU_26M		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_AON_TMR		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_POWER_CPU		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_AP_AXI		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_SDIO0_2X		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_SDIO1_2X		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_SDIO2_2X		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_EMMC_2X		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_DPU			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_DPU_DPI		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_OTG_REF		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_SDPHY_APB		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_ALG_IO_APB		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_GPU_CORE		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_GPU_SOC		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_MM_EMC		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_MM_AHB		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_BPC			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_DCAM_IF		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_ISP			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_JPG			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_CPP			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_SENSOR0		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_SENSOR1		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_SENSOR2		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_MM_VEMC		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_MM_VAHB		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_VSP			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_CORE0		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_CORE1		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_CORE2		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_CORE3		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_CORE4		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_CORE5		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_CORE6		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_CORE7		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_SCU			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_ACE			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_AXI_PERIPH		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_AXI_ACP		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_ATB			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_DEBUG_APB		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_GIC			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_PERIPH		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_AON_CLK_NUM		(CLK_VSP + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_OTG_EB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_DMA_EB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_CE_EB		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_NANDC_EB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_SDIO0_EB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_SDIO1_EB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_SDIO2_EB		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_EMMC_EB		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define CLK_EMMC_32K_EB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_SDIO0_32K_EB	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_SDIO1_32K_EB	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_SDIO2_32K_EB	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_NANDC_26M_EB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_DMA_EB2		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_CE_EB2		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLK_AP_AHB_GATE_NUM	(CLK_CE_EB2 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_GPIO_EB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_PWM0_EB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_PWM1_EB		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_PWM2_EB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define CLK_PWM3_EB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_KPD_EB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_AON_SYST_EB		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_AP_SYST_EB		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define CLK_AON_TMR_EB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_EFUSE_EB		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_EIC_EB		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_INTC_EB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_ADI_EB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_AUDIF_EB		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define CLK_AUD_EB		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_VBC_EB		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_PIN_EB		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_AP_WDG_EB		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_MM_EB		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_AON_APB_CKG_EB	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define CLK_CA53_TS0_EB		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_CA53_TS1_EB		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define CLK_CS53_DAP_EB		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define CLK_PMU_EB		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define CLK_THM_EB		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define CLK_AUX0_EB		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define CLK_AUX1_EB		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define CLK_AUX2_EB		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_PROBE_EB		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_EMC_REF_EB		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define CLK_CA53_WDG_EB		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define CLK_AP_TMR1_EB		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define CLK_AP_TMR2_EB		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define CLK_DISP_EMC_EB		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define CLK_ZIP_EMC_EB		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define CLK_GSP_EMC_EB		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define CLK_MM_VSP_EB		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define CLK_MDAR_EB		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define CLK_RTC4M0_CAL_EB	38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define CLK_RTC4M1_CAL_EB	39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define CLK_DJTAG_EB		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define CLK_MBOX_EB		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define CLK_AON_DMA_EB		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define CLK_AON_APB_DEF_EB	43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define CLK_CA5_TS0_EB		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define CLK_DBG_EB		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define CLK_DBG_EMC_EB		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define CLK_CROSS_TRIG_EB	47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define CLK_SERDES_DPHY_EB	48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define CLK_ARCH_RTC_EB		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define CLK_KPD_RTC_EB		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define CLK_AON_SYST_RTC_EB	51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define CLK_AP_SYST_RTC_EB	52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define CLK_AON_TMR_RTC_EB	53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define CLK_AP_TMR0_RTC_EB	54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define CLK_EIC_RTC_EB		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define CLK_EIC_RTCDV5_EB	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define CLK_AP_WDG_RTC_EB	57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define CLK_CA53_WDG_RTC_EB	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define CLK_THM_RTC_EB		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define CLK_ATHMA_RTC_EB	60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_GTHMA_RTC_EB	61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define CLK_ATHMA_RTC_A_EB	62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define CLK_GTHMA_RTC_A_EB	63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define CLK_AP_TMR1_RTC_EB	64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define CLK_AP_TMR2_RTC_EB	65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define CLK_DXCO_LC_RTC_EB	66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define CLK_BB_CAL_RTC_EB	67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define CLK_GNU_EB		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define CLK_DISP_EB		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define CLK_MM_EMC_EB		70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define CLK_POWER_CPU_EB	71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define CLK_HW_I2C_EB		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define CLK_MM_VSP_EMC_EB	73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define CLK_VSP_EB		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define CLK_CSSYS_EB		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define CLK_DMC_EB		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define CLK_ROSC_EB		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define CLK_S_D_CFG_EB		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define CLK_S_D_REF_EB		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define CLK_B_DMA_EB		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_ANLG_EB		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define CLK_ANLG_APB_EB		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define CLK_BSMTMR_EB		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_AP_AXI_EB		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define CLK_AP_INTC0_EB		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define CLK_AP_INTC1_EB		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define CLK_AP_INTC2_EB		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define CLK_AP_INTC3_EB		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define CLK_AP_INTC4_EB		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define CLK_AP_INTC5_EB		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CLK_SCC_EB		91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define CLK_DPHY_CFG_EB		92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define CLK_DPHY_REF_EB		93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define CLK_CPHY_CFG_EB		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define CLK_OTG_REF_EB		95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define CLK_SERDES_EB		96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define CLK_AON_AP_EMC_EB	97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define CLK_AON_APB_GATE_NUM	(CLK_AON_AP_EMC_EB + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define CLK_MAHB_CKG_EB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define CLK_MDCAM_EB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define CLK_MISP_EB		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define CLK_MAHBCSI_EB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define CLK_MCSI_S_EB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CLK_MCSI_T_EB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define CLK_DCAM_AXI_EB		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define CLK_ISP_AXI_EB		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define CLK_MCSI_EB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define CLK_MCSI_S_CKG_EB	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define CLK_MCSI_T_CKG_EB	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define CLK_SENSOR0_EB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define CLK_SENSOR1_EB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CLK_SENSOR2_EB		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define CLK_MCPHY_CFG_EB	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define CLK_MM_GATE_NUM		(CLK_MCPHY_CFG_EB + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define CLK_MIPI_CSI		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define CLK_MIPI_CSI_S		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define CLK_MIPI_CSI_M		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define CLK_MM_CLK_NUM		(CLK_MIPI_CSI_M + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define CLK_SIM0_EB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define CLK_IIS0_EB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define CLK_IIS1_EB		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define CLK_IIS2_EB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define CLK_SPI0_EB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define CLK_SPI1_EB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define CLK_SPI2_EB		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define CLK_I2C0_EB		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define CLK_I2C1_EB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define CLK_I2C2_EB		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define CLK_I2C3_EB		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define CLK_I2C4_EB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define CLK_UART0_EB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define CLK_UART1_EB		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define CLK_UART2_EB		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define CLK_UART3_EB		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define CLK_UART4_EB		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define CLK_SIM0_32K_EB		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define CLK_SPI3_EB		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define CLK_I2C5_EB		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define CLK_I2C6_EB		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define CLK_AP_APB_GATE_NUM	(CLK_I2C6_EB + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #endif /* _DT_BINDINGS_CLK_SC9863A_H_ */