Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) // SPDX-License-Identifier: (GPL-2.0+ OR MIT)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3) // Spreadtrum SC9860 platform clocks
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4) //
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5) // Copyright (C) 2017, Spreadtrum Communications Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLK_SC9860_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLK_SC9860_H_
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) #define	CLK_FAC_4M		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define	CLK_FAC_2M		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define	CLK_FAC_1M		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define	CLK_FAC_250K		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define	CLK_FAC_RPLL0_26M	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) #define	CLK_FAC_RPLL1_26M	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) #define	CLK_FAC_RCO25M		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define	CLK_FAC_RCO4M		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define	CLK_FAC_RCO2M		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define	CLK_FAC_3K2		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define	CLK_FAC_1K		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define	CLK_MPLL0_GATE		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define	CLK_MPLL1_GATE		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define	CLK_DPLL0_GATE		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define	CLK_DPLL1_GATE		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define	CLK_LTEPLL0_GATE	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define	CLK_TWPLL_GATE		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define	CLK_LTEPLL1_GATE	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define	CLK_RPLL0_GATE		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define	CLK_RPLL1_GATE		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define	CLK_CPPLL_GATE		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define	CLK_GPLL_GATE		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define CLK_PMU_GATE_NUM	(CLK_GPLL_GATE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define	CLK_MPLL0		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define	CLK_MPLL1		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define	CLK_DPLL0		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define	CLK_DPLL1		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define	CLK_RPLL0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define	CLK_RPLL1		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define	CLK_TWPLL		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define	CLK_LTEPLL0		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define	CLK_LTEPLL1		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define	CLK_GPLL		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define	CLK_CPPLL		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define	CLK_GPLL_42M5		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define	CLK_TWPLL_768M		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define	CLK_TWPLL_384M		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define	CLK_TWPLL_192M		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define	CLK_TWPLL_96M		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define	CLK_TWPLL_48M		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define	CLK_TWPLL_24M		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define	CLK_TWPLL_12M		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define	CLK_TWPLL_512M		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define	CLK_TWPLL_256M		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define	CLK_TWPLL_128M		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define	CLK_TWPLL_64M		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define	CLK_TWPLL_307M2		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define	CLK_TWPLL_153M6		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define	CLK_TWPLL_76M8		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define	CLK_TWPLL_51M2		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define	CLK_TWPLL_38M4		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define	CLK_TWPLL_19M2		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define	CLK_L0_614M4		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define	CLK_L0_409M6		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define	CLK_L0_38M		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define	CLK_L1_38M		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define	CLK_RPLL0_192M		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define	CLK_RPLL0_96M		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define	CLK_RPLL0_48M		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define	CLK_RPLL1_468M		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define	CLK_RPLL1_192M		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define	CLK_RPLL1_96M		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define	CLK_RPLL1_64M		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define	CLK_RPLL1_48M		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define	CLK_DPLL0_50M		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define	CLK_DPLL1_50M		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define	CLK_CPPLL_50M		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define	CLK_M0_39M		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define	CLK_M1_63M		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) #define CLK_PLL_NUM		(CLK_M1_63M + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define	CLK_AP_APB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) #define	CLK_AP_USB3		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) #define	CLK_UART0		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define	CLK_UART1		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define	CLK_UART2		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define	CLK_UART3		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define	CLK_UART4		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define	CLK_I2C0		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define	CLK_I2C1		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define	CLK_I2C2		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define	CLK_I2C3		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define	CLK_I2C4		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define	CLK_I2C5		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define	CLK_SPI0		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define	CLK_SPI1		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define	CLK_SPI2		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define	CLK_SPI3		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define	CLK_IIS0		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define	CLK_IIS1		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define	CLK_IIS2		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define	CLK_IIS3		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_AP_CLK_NUM		(CLK_IIS3 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define	CLK_AON_APB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define	CLK_AUX0		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define	CLK_AUX1		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define	CLK_AUX2		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define	CLK_PROBE		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define	CLK_SP_AHB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define	CLK_CCI			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define	CLK_GIC			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define	CLK_CSSYS		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define	CLK_SDIO0_2X		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define	CLK_SDIO1_2X		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define	CLK_SDIO2_2X		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define	CLK_EMMC_2X		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define	CLK_SDIO0_1X		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define	CLK_SDIO1_1X		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define	CLK_SDIO2_1X		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define	CLK_EMMC_1X		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define	CLK_ADI			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define	CLK_PWM0		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define	CLK_PWM1		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define	CLK_PWM2		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define	CLK_PWM3		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define	CLK_EFUSE		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define	CLK_CM3_UART0		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define	CLK_CM3_UART1		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define	CLK_THM			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define	CLK_CM3_I2C0		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define	CLK_CM3_I2C1		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define	CLK_CM4_SPI		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define	CLK_AON_I2C		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define	CLK_AVS			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define	CLK_CA53_DAP		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define	CLK_CA53_TS		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define	CLK_DJTAG_TCK		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define	CLK_PMU			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define	CLK_PMU_26M		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define	CLK_DEBOUNCE		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define	CLK_OTG2_REF		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define	CLK_USB3_REF		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define	CLK_AP_AXI		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_AON_PREDIV_NUM	(CLK_AP_AXI + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define	CLK_USB3_EB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define	CLK_USB3_SUSPEND_EB	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define	CLK_USB3_REF_EB		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define	CLK_DMA_EB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define	CLK_SDIO0_EB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define	CLK_SDIO1_EB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define	CLK_SDIO2_EB		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define	CLK_EMMC_EB		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define	CLK_ROM_EB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define	CLK_BUSMON_EB		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define	CLK_CC63S_EB		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define	CLK_CC63P_EB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define	CLK_CE0_EB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define	CLK_CE1_EB		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_APAHB_GATE_NUM	(CLK_CE1_EB + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define	CLK_AVS_LIT_EB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define	CLK_AVS_BIG_EB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define	CLK_AP_INTC5_EB		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define	CLK_GPIO_EB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define	CLK_PWM0_EB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define	CLK_PWM1_EB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define	CLK_PWM2_EB		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define	CLK_PWM3_EB		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define	CLK_KPD_EB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define	CLK_AON_SYS_EB		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define	CLK_AP_SYS_EB		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define	CLK_AON_TMR_EB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define	CLK_AP_TMR0_EB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define	CLK_EFUSE_EB		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define	CLK_EIC_EB		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define	CLK_PUB1_REG_EB		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define	CLK_ADI_EB		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define	CLK_AP_INTC0_EB		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define	CLK_AP_INTC1_EB		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define	CLK_AP_INTC2_EB		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define	CLK_AP_INTC3_EB		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define	CLK_AP_INTC4_EB		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define	CLK_SPLK_EB		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define	CLK_MSPI_EB		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define	CLK_PUB0_REG_EB		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define	CLK_PIN_EB		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define	CLK_AON_CKG_EB		26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define	CLK_GPU_EB		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define	CLK_APCPU_TS0_EB	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define	CLK_APCPU_TS1_EB	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define	CLK_DAP_EB		30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define	CLK_I2C_EB		31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define	CLK_PMU_EB		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define	CLK_THM_EB		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define	CLK_AUX0_EB		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define	CLK_AUX1_EB		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define	CLK_AUX2_EB		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define	CLK_PROBE_EB		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define	CLK_GPU0_AVS_EB		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define	CLK_GPU1_AVS_EB		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define	CLK_APCPU_WDG_EB	40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define	CLK_AP_TMR1_EB		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define	CLK_AP_TMR2_EB		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define	CLK_DISP_EMC_EB		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define	CLK_ZIP_EMC_EB		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define	CLK_GSP_EMC_EB		45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define	CLK_OSC_AON_EB		46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define	CLK_LVDS_TRX_EB		47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define	CLK_LVDS_TCXO_EB	48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define	CLK_MDAR_EB		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define	CLK_RTC4M0_CAL_EB	50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define	CLK_RCT100M_CAL_EB	51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define	CLK_DJTAG_EB		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define	CLK_MBOX_EB		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define	CLK_AON_DMA_EB		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define	CLK_DBG_EMC_EB		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define	CLK_LVDS_PLL_DIV_EN	56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define	CLK_DEF_EB		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define	CLK_AON_APB_RSV0	58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define	CLK_ORP_JTAG_EB		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define	CLK_VSP_EB		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define	CLK_CAM_EB		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define	CLK_DISP_EB		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define	CLK_DBG_AXI_IF_EB	63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define	CLK_SDIO0_2X_EN		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define	CLK_SDIO1_2X_EN		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define	CLK_SDIO2_2X_EN		66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define	CLK_EMMC_2X_EN		67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define	CLK_ARCH_RTC_EB		68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define	CLK_KPB_RTC_EB		69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define	CLK_AON_SYST_RTC_EB	70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define	CLK_AP_SYST_RTC_EB	71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define	CLK_AON_TMR_RTC_EB	72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define	CLK_AP_TMR0_RTC_EB	73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define	CLK_EIC_RTC_EB		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define	CLK_EIC_RTCDV5_EB	75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define	CLK_AP_WDG_RTC_EB	76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define	CLK_AP_TMR1_RTC_EB	77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define	CLK_AP_TMR2_RTC_EB	78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define	CLK_DCXO_TMR_RTC_EB	79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define	CLK_BB_CAL_RTC_EB	80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define	CLK_AVS_BIG_RTC_EB	81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define	CLK_AVS_LIT_RTC_EB	82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define	CLK_AVS_GPU0_RTC_EB	83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define	CLK_AVS_GPU1_RTC_EB	84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define	CLK_GPU_TS_EB		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define	CLK_RTCDV10_EB		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define	CLK_AON_GATE_NUM	(CLK_RTCDV10_EB + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define	CLK_LIT_MCU		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define	CLK_BIG_MCU		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define CLK_AONSECURE_NUM	(CLK_BIG_MCU + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define	CLK_AGCP_IIS0_EB	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define	CLK_AGCP_IIS1_EB	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define	CLK_AGCP_IIS2_EB	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define	CLK_AGCP_IIS3_EB	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define	CLK_AGCP_UART_EB	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define	CLK_AGCP_DMACP_EB	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define	CLK_AGCP_DMAAP_EB	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define	CLK_AGCP_ARC48K_EB	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define	CLK_AGCP_SRC44P1K_EB	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define	CLK_AGCP_MCDT_EB	9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define	CLK_AGCP_VBCIFD_EB	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define	CLK_AGCP_VBC_EB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define	CLK_AGCP_SPINLOCK_EB	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define	CLK_AGCP_ICU_EB		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define	CLK_AGCP_AP_ASHB_EB	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define	CLK_AGCP_CP_ASHB_EB	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define	CLK_AGCP_AUD_EB		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define	CLK_AGCP_AUDIF_EB	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define CLK_AGCP_GATE_NUM	(CLK_AGCP_AUDIF_EB + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define	CLK_GPU			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define CLK_GPU_NUM		(CLK_GPU + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define	CLK_AHB_VSP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define	CLK_VSP			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define	CLK_VSP_ENC		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define	CLK_VPP			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define	CLK_VSP_26M		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define CLK_VSP_NUM		(CLK_VSP_26M + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define	CLK_VSP_DEC_EB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define	CLK_VSP_CKG_EB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define	CLK_VSP_MMU_EB		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define	CLK_VSP_ENC_EB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define	CLK_VPP_EB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define	CLK_VSP_26M_EB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define	CLK_VSP_AXI_GATE	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define	CLK_VSP_ENC_GATE	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define	CLK_VPP_AXI_GATE	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define	CLK_VSP_BM_GATE		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define	CLK_VSP_ENC_BM_GATE	10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define	CLK_VPP_BM_GATE		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define CLK_VSP_GATE_NUM	(CLK_VPP_BM_GATE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define	CLK_AHB_CAM		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define	CLK_SENSOR0		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define	CLK_SENSOR1		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define	CLK_SENSOR2		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define	CLK_MIPI_CSI0_EB	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define	CLK_MIPI_CSI1_EB	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) #define CLK_CAM_NUM		(CLK_MIPI_CSI1_EB + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define	CLK_DCAM0_EB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define	CLK_DCAM1_EB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define	CLK_ISP0_EB		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define	CLK_CSI0_EB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define	CLK_CSI1_EB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define	CLK_JPG0_EB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define	CLK_JPG1_EB		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define	CLK_CAM_CKG_EB		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define	CLK_CAM_MMU_EB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define	CLK_ISP1_EB		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define	CLK_CPP_EB		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define	CLK_MMU_PF_EB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define	CLK_ISP2_EB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define	CLK_DCAM2ISP_IF_EB	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define	CLK_ISP2DCAM_IF_EB	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define	CLK_ISP_LCLK_EB		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define	CLK_ISP_ICLK_EB		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define	CLK_ISP_MCLK_EB		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define	CLK_ISP_PCLK_EB		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define	CLK_ISP_ISP2DCAM_EB	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define	CLK_DCAM0_IF_EB		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define	CLK_CLK26M_IF_EB	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define	CLK_CPHY0_GATE		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define	CLK_MIPI_CSI0_GATE	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define	CLK_CPHY1_GATE		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define	CLK_MIPI_CSI1		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define	CLK_DCAM0_AXI_GATE	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define	CLK_DCAM1_AXI_GATE	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define	CLK_SENSOR0_GATE	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define	CLK_SENSOR1_GATE	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define	CLK_JPG0_AXI_GATE	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define	CLK_GPG1_AXI_GATE	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define	CLK_ISP0_AXI_GATE	32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define	CLK_ISP1_AXI_GATE	33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define	CLK_ISP2_AXI_GATE	34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define	CLK_CPP_AXI_GATE	35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define	CLK_D0_IF_AXI_GATE	36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define	CLK_D2I_IF_AXI_GATE	37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define	CLK_I2D_IF_AXI_GATE	38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define	CLK_SPARE_AXI_GATE	39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define	CLK_SENSOR2_GATE	40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define	CLK_D0IF_IN_D_EN	41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define	CLK_D1IF_IN_D_EN	42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define	CLK_D0IF_IN_D2I_EN	43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define	CLK_D1IF_IN_D2I_EN	44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define	CLK_IA_IN_D2I_EN	45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define	CLK_IB_IN_D2I_EN	46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356) #define	CLK_IC_IN_D2I_EN	47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define	CLK_IA_IN_I_EN		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358) #define	CLK_IB_IN_I_EN		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) #define	CLK_IC_IN_I_EN		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360) #define CLK_CAM_GATE_NUM	(CLK_IC_IN_I_EN + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define	CLK_AHB_DISP		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define	CLK_DISPC0_DPI		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define	CLK_DISPC1_DPI		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define CLK_DISP_NUM		(CLK_DISPC1_DPI + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define	CLK_DISPC0_EB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define	CLK_DISPC1_EB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define	CLK_DISPC_MMU_EB	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define	CLK_GSP0_EB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define	CLK_GSP1_EB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define	CLK_GSP0_MMU_EB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define	CLK_GSP1_MMU_EB		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define	CLK_DSI0_EB		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define	CLK_DSI1_EB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376) #define	CLK_DISP_CKG_EB		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) #define	CLK_DISP_GPU_EB		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define	CLK_GPU_MTX_EB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define	CLK_GSP_MTX_EB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define	CLK_TMC_MTX_EB		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define	CLK_DISPC_MTX_EB	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define	CLK_DPHY0_GATE		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define	CLK_DPHY1_GATE		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define	CLK_GSP0_A_GATE		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define	CLK_GSP1_A_GATE		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define	CLK_GSP0_F_GATE		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387) #define	CLK_GSP1_F_GATE		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) #define	CLK_D_MTX_F_GATE	21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389) #define	CLK_D_MTX_A_GATE	22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) #define	CLK_D_NOC_F_GATE	23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define	CLK_D_NOC_A_GATE	24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define	CLK_GSP_MTX_F_GATE	25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define	CLK_GSP_MTX_A_GATE	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define	CLK_GSP_NOC_F_GATE	27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define	CLK_GSP_NOC_A_GATE	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define	CLK_DISPM0IDLE_GATE	29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define	CLK_GSPM0IDLE_GATE	30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define CLK_DISP_GATE_NUM	(CLK_GSPM0IDLE_GATE + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define	CLK_SIM0_EB		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define	CLK_IIS0_EB		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define	CLK_IIS1_EB		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define	CLK_IIS2_EB		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define	CLK_IIS3_EB		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define	CLK_SPI0_EB		5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define	CLK_SPI1_EB		6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407) #define	CLK_SPI2_EB		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) #define	CLK_I2C0_EB		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define	CLK_I2C1_EB		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define	CLK_I2C2_EB		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define	CLK_I2C3_EB		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define	CLK_I2C4_EB		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define	CLK_I2C5_EB		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define	CLK_UART0_EB		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define	CLK_UART1_EB		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define	CLK_UART2_EB		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define	CLK_UART3_EB		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define	CLK_UART4_EB		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define	CLK_AP_CKG_EB		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define	CLK_SPI3_EB		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define CLK_APAPB_GATE_NUM	(CLK_SPI3_EB + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423) #endif /* _DT_BINDINGS_CLK_SC9860_H_ */