^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0 OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (C) 2018-2019 SiFive, Inc.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Wesley Terpstra
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Paul Walmsley
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define __DT_BINDINGS_CLOCK_SIFIVE_FU540_PRCI_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /* Clock indexes for use by Device Tree data and the PRCI driver */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PRCI_CLK_COREPLL 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define PRCI_CLK_DDRPLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define PRCI_CLK_GEMGXLPLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define PRCI_CLK_TLCLK 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #endif