Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0-or-later */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright 2014 Ulrich Hecht
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6) #ifndef __DT_BINDINGS_CLOCK_SH73A0_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) #define __DT_BINDINGS_CLOCK_SH73A0_H__
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) /* CPG */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define SH73A0_CLK_MAIN		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) #define SH73A0_CLK_PLL0		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #define SH73A0_CLK_PLL1		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define SH73A0_CLK_PLL2		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define SH73A0_CLK_PLL3		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define SH73A0_CLK_DSI0PHY	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define SH73A0_CLK_DSI1PHY	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define SH73A0_CLK_ZG		7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define SH73A0_CLK_M3		8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define SH73A0_CLK_B		9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define SH73A0_CLK_M1		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define SH73A0_CLK_M2		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SH73A0_CLK_Z		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SH73A0_CLK_ZX		13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SH73A0_CLK_HP		14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) /* MSTP0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define SH73A0_CLK_IIC2		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define SH73A0_CLK_MSIOF0	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* MSTP1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SH73A0_CLK_CEU1		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SH73A0_CLK_CSI2_RX1	28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SH73A0_CLK_CEU0		27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SH73A0_CLK_CSI2_RX0	26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SH73A0_CLK_TMU0		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SH73A0_CLK_DSITX0	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SH73A0_CLK_IIC0		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SH73A0_CLK_SGX		12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define SH73A0_CLK_LCDC0	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) /* MSTP2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define SH73A0_CLK_SCIFA7	19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define SH73A0_CLK_SY_DMAC	18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define SH73A0_CLK_MP_DMAC	17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define SH73A0_CLK_MSIOF3	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define SH73A0_CLK_MSIOF1	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define SH73A0_CLK_SCIFA5	7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define SH73A0_CLK_SCIFB	6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define SH73A0_CLK_MSIOF2	5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define SH73A0_CLK_SCIFA0	4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define SH73A0_CLK_SCIFA1	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define SH73A0_CLK_SCIFA2	2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define SH73A0_CLK_SCIFA3	1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define SH73A0_CLK_SCIFA4	0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) /* MSTP3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define SH73A0_CLK_SCIFA6	31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define SH73A0_CLK_CMT1		29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define SH73A0_CLK_FSI		28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define SH73A0_CLK_IRDA		25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define SH73A0_CLK_IIC1		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define SH73A0_CLK_USB		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define SH73A0_CLK_FLCTL	15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define SH73A0_CLK_SDHI0	14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define SH73A0_CLK_SDHI1	13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define SH73A0_CLK_MMCIF0	12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define SH73A0_CLK_SDHI2	11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define SH73A0_CLK_TPU0		4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define SH73A0_CLK_TPU1		3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define SH73A0_CLK_TPU2		2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define SH73A0_CLK_TPU3		1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define SH73A0_CLK_TPU4		0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) /* MSTP4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define SH73A0_CLK_IIC3		11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define SH73A0_CLK_IIC4		10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define SH73A0_CLK_KEYSC	3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) /* MSTP5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SH73A0_CLK_INTCA0	8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #endif