^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Tomasz Figa <tomasz.figa at gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * Device Tree binding constants for Samsung S3C64xx clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) * Let each exported clock get a unique index, which is used on DT-enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) * platforms to lookup the clock from a clock specifier. These indices are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) * therefore considered an ABI and so must not be changed. This implies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) * that new clocks should be added either in free spaces between clock groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) * or at the end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Core clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK27M 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK48M 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define FOUT_APLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define FOUT_MPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define FOUT_EPLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define ARMCLK 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define HCLKX2 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HCLK 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCLK 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) /* HCLK bus clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define HCLK_3DSE 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define HCLK_UHOST 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define HCLK_SECUR 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define HCLK_SDMA1 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define HCLK_SDMA0 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define HCLK_IROM 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define HCLK_DDR1 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define HCLK_MEM1 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define HCLK_MEM0 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define HCLK_USB 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define HCLK_HSMMC2 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define HCLK_HSMMC1 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define HCLK_HSMMC0 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define HCLK_MDP 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define HCLK_DHOST 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define HCLK_IHOST 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HCLK_DMA1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HCLK_DMA0 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HCLK_JPEG 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HCLK_CAMIF 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HCLK_SCALER 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HCLK_2D 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HCLK_TV 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HCLK_POST0 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HCLK_ROT 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HCLK_LCD 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HCLK_TZIC 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HCLK_INTC 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HCLK_MFC 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HCLK_DDR0 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) /* PCLK bus clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define PCLK_IIC1 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define PCLK_IIS2 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define PCLK_SKEY 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PCLK_CHIPID 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PCLK_SPI1 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCLK_SPI0 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCLK_HSIRX 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCLK_HSITX 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCLK_GPIO 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCLK_IIC0 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCLK_IIS1 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCLK_IIS0 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCLK_AC97 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCLK_TZPC 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCLK_TSADC 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCLK_KEYPAD 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCLK_IRDA 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCLK_PCM1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCLK_PCM0 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCLK_PWM 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCLK_RTC 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCLK_WDT 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCLK_UART3 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCLK_UART2 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define PCLK_UART1 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define PCLK_UART0 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define PCLK_MFC 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) /* Special clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SCLK_UHOST 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SCLK_MMC2_48 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SCLK_MMC1_48 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SCLK_MMC0_48 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SCLK_MMC2 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SCLK_MMC1 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SCLK_MMC0 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SCLK_SPI1_48 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define SCLK_SPI0_48 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define SCLK_SPI1 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define SCLK_SPI0 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define SCLK_DAC27 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SCLK_TV27 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define SCLK_SCALER27 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define SCLK_SCALER 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define SCLK_LCD27 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define SCLK_LCD 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define SCLK_FIMC 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define SCLK_POST0_27 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define SCLK_AUDIO2 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define SCLK_POST0 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define SCLK_AUDIO1 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define SCLK_AUDIO0 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define SCLK_SECUR 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define SCLK_IRDA 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define SCLK_UART 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define SCLK_MFC 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define SCLK_CAM 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define SCLK_JPEG 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define SCLK_ONENAND 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) /* MEM0 bus clocks - S3C6410-specific. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define MEM0_CFCON 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MEM0_ONENAND1 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MEM0_ONENAND0 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MEM0_NFCON 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MEM0_SROM 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) /* Muxes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MOUT_APLL 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MOUT_MPLL 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MOUT_EPLL 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MOUT_MFC 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MOUT_AUDIO0 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MOUT_AUDIO1 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MOUT_UART 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MOUT_SPI0 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MOUT_SPI1 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MOUT_MMC0 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MOUT_MMC1 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MOUT_MMC2 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MOUT_UHOST 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MOUT_IRDA 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MOUT_LCD 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define MOUT_SCALER 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define MOUT_DAC27 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define MOUT_TV27 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define MOUT_AUDIO2 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) /* Dividers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define DOUT_MPLL 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define DOUT_SECUR 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define DOUT_CAM 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define DOUT_JPEG 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define DOUT_MFC 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define DOUT_MMC0 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define DOUT_MMC1 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define DOUT_MMC2 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define DOUT_LCD 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define DOUT_SCALER 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define DOUT_UHOST 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define DOUT_SPI0 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define DOUT_SPI1 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define DOUT_AUDIO0 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define DOUT_AUDIO1 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define DOUT_UART 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define DOUT_IRDA 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define DOUT_FIMC 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define DOUT_AUDIO2 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) /* Total number of clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define NR_CLKS (DOUT_AUDIO2 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C64XX_CLOCK_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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