^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2013 Samsung Electronics Co., Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Mateusz Krawczuk <m.krawczuk@partner.samsung.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * Device Tree binding constants for Samsung S5PV210 clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) #ifndef _DT_BINDINGS_CLOCK_S5PV210_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) #define _DT_BINDINGS_CLOCK_S5PV210_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* Core clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define FIN_PLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14) #define FOUT_APLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define FOUT_MPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define FOUT_EPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define FOUT_VPLL 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Muxes. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MOUT_FLASH 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define MOUT_PSYS 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MOUT_DSYS 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define MOUT_MSYS 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MOUT_VPLL 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MOUT_EPLL 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MOUT_MPLL 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define MOUT_APLL 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define MOUT_VPLLSRC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define MOUT_CSIS 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define MOUT_FIMD 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define MOUT_CAM1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define MOUT_CAM0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define MOUT_DAC 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define MOUT_MIXER 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define MOUT_HDMI 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define MOUT_G2D 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define MOUT_MFC 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define MOUT_G3D 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define MOUT_FIMC2 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define MOUT_FIMC1 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MOUT_FIMC0 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MOUT_UART3 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MOUT_UART2 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MOUT_UART1 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define MOUT_UART0 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define MOUT_MMC3 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define MOUT_MMC2 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define MOUT_MMC1 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define MOUT_MMC0 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define MOUT_PWM 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define MOUT_SPI0 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define MOUT_SPI1 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define MOUT_DMC0 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define MOUT_PWI 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define MOUT_HPM 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define MOUT_SPDIF 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define MOUT_AUDIO2 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define MOUT_AUDIO1 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define MOUT_AUDIO0 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) /* Dividers. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define DOUT_PCLKP 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define DOUT_HCLKP 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define DOUT_PCLKD 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define DOUT_HCLKD 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define DOUT_PCLKM 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define DOUT_HCLKM 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define DOUT_A2M 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define DOUT_APLL 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define DOUT_CSIS 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define DOUT_FIMD 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define DOUT_CAM1 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define DOUT_CAM0 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define DOUT_TBLK 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define DOUT_G2D 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define DOUT_MFC 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define DOUT_G3D 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define DOUT_FIMC2 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define DOUT_FIMC1 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define DOUT_FIMC0 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define DOUT_UART3 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define DOUT_UART2 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define DOUT_UART1 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define DOUT_UART0 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define DOUT_MMC3 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define DOUT_MMC2 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define DOUT_MMC1 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define DOUT_MMC0 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define DOUT_PWM 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define DOUT_SPI1 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define DOUT_SPI0 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define DOUT_DMC0 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define DOUT_PWI 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define DOUT_HPM 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define DOUT_COPY 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define DOUT_FLASH 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define DOUT_AUDIO2 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define DOUT_AUDIO1 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define DOUT_AUDIO0 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define DOUT_DPM 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define DOUT_DVSEM 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) /* Gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define SCLK_FIMC 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_CSIS 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_ROTATOR 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define CLK_FIMC2 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define CLK_FIMC1 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define CLK_FIMC0 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define CLK_MFC 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_G2D 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_G3D 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_IMEM 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_PDMA1 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_PDMA0 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_MDMA 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_DMC1 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_DMC0 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_NFCON 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_SROMC 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_CFCON 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_NANDXL 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_USB_HOST 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_USB_OTG 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define CLK_HDMI 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define CLK_TVENC 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define CLK_MIXER 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define CLK_VP 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define CLK_DSIM 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define CLK_FIMD 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define CLK_TZIC3 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define CLK_TZIC2 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define CLK_TZIC1 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define CLK_TZIC0 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define CLK_VIC3 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define CLK_VIC2 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define CLK_VIC1 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define CLK_VIC0 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define CLK_TSI 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define CLK_HSMMC3 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define CLK_HSMMC2 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define CLK_HSMMC1 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define CLK_HSMMC0 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define CLK_JTAG 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define CLK_MODEMIF 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define CLK_CORESIGHT 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define CLK_SDM 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define CLK_SECSS 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define CLK_PCM2 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_PCM1 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_PCM0 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_SYSCON 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_GPIO 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_TSADC 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_PWM 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_WDT 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_KEYIF 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_UART3 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_UART2 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_UART1 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_UART0 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_SYSTIMER 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_RTC 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_SPI1 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_SPI0 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_I2C_HDMI_PHY 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_I2C1 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_I2C2 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_I2C0 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_I2S1 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_I2S2 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_I2S0 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_AC97 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_SPDIF 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_TZPC3 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define CLK_TZPC2 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define CLK_TZPC1 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_TZPC0 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define CLK_SECKEY 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define CLK_IEM_APC 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_IEM_IEC 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define CLK_CHIPID 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define CLK_JPEG 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) /* Special clocks*/
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define SCLK_PWI 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define SCLK_SPDIF 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define SCLK_AUDIO2 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define SCLK_AUDIO1 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define SCLK_AUDIO0 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define SCLK_PWM 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define SCLK_SPI1 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define SCLK_SPI0 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define SCLK_UART3 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define SCLK_UART2 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SCLK_UART1 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define SCLK_UART0 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define SCLK_MMC3 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define SCLK_MMC2 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define SCLK_MMC1 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define SCLK_MMC0 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define SCLK_FINVPLL 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define SCLK_CSIS 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define SCLK_FIMD 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define SCLK_CAM1 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define SCLK_CAM0 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define SCLK_DAC 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define SCLK_MIXER 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SCLK_HDMI 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define SCLK_FIMC2 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SCLK_FIMC1 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define SCLK_FIMC0 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define SCLK_HDMI27M 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SCLK_HDMIPHY 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define SCLK_USBPHY0 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SCLK_USBPHY1 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) /* S5P6442-specific clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define MOUT_D0SYNC 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define MOUT_D1SYNC 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DOUT_MIXER 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define CLK_ETB 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define CLK_ETM 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) /* CLKOUT */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define FOUT_APLL_CLKOUT 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define FOUT_MPLL_CLKOUT 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define DOUT_APLL_CLKOUT 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define MOUT_CLKSEL 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define DOUT_CLKOUT 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define MOUT_CLKOUT 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) /* Total number of clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define NR_CLKS 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #endif /* _DT_BINDINGS_CLOCK_S5PV210_H */
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
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