^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: GPL-2.0-only */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2014 Tomasz Figa <tomasz.figa@gmail.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) * This header provides constants for Samsung audio subsystem
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6) * clock controller.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) * The constants defined in this header are being used in dts
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9) * and s5pv210 audss driver.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) #ifndef _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define _DT_BINDINGS_CLOCK_S5PV210_AUDSS_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) #define CLK_MOUT_AUDSS 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_MOUT_I2S_A 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_DOUT_AUD_BUS 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_DOUT_I2S_A 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_I2S 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define CLK_HCLK_I2S 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define CLK_HCLK_UART 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define CLK_HCLK_HWA 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define CLK_HCLK_DMA 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_HCLK_BUF 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_HCLK_RP 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define AUDSS_MAX_CLKS 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #endif