Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Device Tree binding constants clock controllers of Samsung S3C2443 and later.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * Let each exported clock get a unique index, which is used on DT-enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * platforms to lookup the clock from a clock specifier. These indices are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * therefore considered an ABI and so must not be changed. This implies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * that new clocks should be added either in free spaces between clock groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * or at the end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Core clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define MSYSCLK			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define ESYSCLK			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define ARMDIV			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define ARMCLK			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define HCLK			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define PCLK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define MPLL			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define EPLL			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) /* Special clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define SCLK_HSSPI0		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define SCLK_FIMD		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define SCLK_I2S0		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define SCLK_I2S1		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCLK_HSMMC1		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SCLK_HSMMC_EXT		21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCLK_CAM		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCLK_UART		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCLK_USBH		24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* Muxes */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define MUX_HSSPI0		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define MUX_HSSPI1		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define MUX_HSMMC0		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define MUX_HSMMC1		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) /* hclk-gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define HCLK_DMA0		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define HCLK_DMA1		49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define HCLK_DMA2		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define HCLK_DMA3		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define HCLK_DMA4		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define HCLK_DMA5		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define HCLK_DMA6		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define HCLK_DMA7		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define HCLK_CAM		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HCLK_LCD		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HCLK_USBH		58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HCLK_USBD		59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HCLK_IROM		60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HCLK_HSMMC0		61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HCLK_HSMMC1		62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HCLK_CFC		63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HCLK_SSMC		64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HCLK_DRAM		65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HCLK_2D			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* pclk-gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PCLK_UART0		72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PCLK_UART1		73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #define PCLK_UART2		74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) #define PCLK_UART3		75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define PCLK_I2C0		76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define PCLK_SDI		77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define PCLK_SPI0		78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define PCLK_ADC		79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define PCLK_AC97		80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define PCLK_I2S0		81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define PCLK_PWM		82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define PCLK_WDT		83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define PCLK_RTC		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define PCLK_GPIO		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define PCLK_SPI1		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define PCLK_CHIPID		87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define PCLK_I2C1		88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define PCLK_I2S1		89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define PCLK_PCM		90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) /* Total number of clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define NR_CLKS			(PCLK_PCM + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2443_CLOCK_H */