Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  1) /* SPDX-License-Identifier: GPL-2.0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  3)  * Copyright (c) 2013 Heiko Stuebner <heiko@sntech.de>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  4)  *
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  5)  * Device Tree binding constants clock controllers of Samsung S3C2412.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  6)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  7) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  8) #ifndef _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  9) #define _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12)  * Let each exported clock get a unique index, which is used on DT-enabled
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13)  * platforms to lookup the clock from a clock specifier. These indices are
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)  * therefore considered an ABI and so must not be changed. This implies
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15)  * that new clocks should be added either in free spaces between clock groups
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16)  * or at the end.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) /* Core clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) /* id 1 is reserved */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define MPLL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define UPLL			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define MDIVCLK			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define MSYSCLK			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define USYSCLK			6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define HCLK			7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define PCLK			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define ARMDIV			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define ARMCLK			10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) /* Special clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define SCLK_CAM		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define SCLK_UART		17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define SCLK_I2S		18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define SCLK_USBD		19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define SCLK_USBH		20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) /* pclk-gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define PCLK_WDT		32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42) #define PCLK_SPI		33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) #define PCLK_I2S		34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCLK_I2C		35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCLK_ADC		36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCLK_RTC		37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCLK_GPIO		38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCLK_UART2		39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCLK_UART1		40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCLK_UART0		41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCLK_SDI		42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCLK_PWM		43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCLK_USBD		44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) /* hclk-gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define HCLK_HALF		48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define HCLK_X2			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define HCLK_SDRAM		50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define HCLK_USBH		51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60) #define HCLK_LCD		52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define HCLK_NAND		53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62) #define HCLK_DMA3		54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) #define HCLK_DMA2		55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64) #define HCLK_DMA1		56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) #define HCLK_DMA0		57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) /* Total number of clocks. */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define NR_CLKS			(HCLK_DMA0 + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70) #endif /* _DT_BINDINGS_CLOCK_SAMSUNG_S3C2412_CLOCK_H */