^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 3) * Copyright (c) 2019 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 4) * Author: Finley Xiao <finley.xiao@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 5) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 6)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 8) #define _DT_BINDINGS_CLK_ROCKCHIP_RV1126_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 9)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 10) /* pmucru-clocks indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 11)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 12) /* pll clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 13) #define PLL_GPLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 14)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 15) /* sclk (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 16) #define CLK_OSC0_DIV32K 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 17) #define CLK_RTC32K 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 18) #define CLK_WIFI_DIV 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 19) #define CLK_WIFI_OSC0 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 20) #define CLK_WIFI 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 21) #define CLK_PMU 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 22) #define SCLK_UART1_DIV 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 23) #define SCLK_UART1_FRACDIV 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 24) #define SCLK_UART1_MUX 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 25) #define SCLK_UART1 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 26) #define CLK_I2C0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 27) #define CLK_I2C2 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 28) #define CLK_CAPTURE_PWM0 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 29) #define CLK_PWM0 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 30) #define CLK_CAPTURE_PWM1 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 31) #define CLK_PWM1 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 32) #define CLK_SPI0 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 33) #define DBCLK_GPIO0 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 34) #define CLK_PMUPVTM 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 35) #define CLK_CORE_PMUPVTM 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 36) #define CLK_REF12M 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 37) #define CLK_USBPHY_OTG_REF 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 38) #define CLK_USBPHY_HOST_REF 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 39) #define CLK_REF24M 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 40) #define CLK_MIPIDSIPHY_REF 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 41) #define CLK_32K_IOE 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 42)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 43) /* pclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 44) #define PCLK_PDPMU 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 45) #define PCLK_PMU 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 46) #define PCLK_UART1 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 47) #define PCLK_I2C0 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 48) #define PCLK_I2C2 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 49) #define PCLK_PWM0 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 50) #define PCLK_PWM1 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 51) #define PCLK_SPI0 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 52) #define PCLK_GPIO0 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 53) #define PCLK_PMUSGRF 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 54) #define PCLK_PMUGRF 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 55) #define PCLK_PMUCRU 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 56) #define PCLK_CHIPVEROTP 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 57) #define PCLK_PDPMU_NIU 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 58) #define PCLK_PMUPVTM 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 59) #define PCLK_SCRKEYGEN 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 60)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 61) #define CLKPMU_NR_CLKS (PCLK_SCRKEYGEN + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 62)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 63) /* cru-clocks indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 64)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 65) /* pll clocks */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 66) #define PLL_APLL 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 67) #define PLL_DPLL 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 68) #define PLL_CPLL 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 69) #define PLL_HPLL 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 70)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 71) /* sclk (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 72) #define ARMCLK 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 73) #define USB480M 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 74) #define CLK_CORE_CPUPVTM 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 75) #define CLK_CPUPVTM 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 76) #define CLK_SCR1 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 77) #define CLK_SCR1_CORE 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 78) #define CLK_SCR1_RTC 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 79) #define CLK_SCR1_JTAG 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 80) #define SCLK_UART0_DIV 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 81) #define SCLK_UART0_FRAC 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 82) #define SCLK_UART0_MUX 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 83) #define SCLK_UART0 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 84) #define SCLK_UART2_DIV 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 85) #define SCLK_UART2_FRAC 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 86) #define SCLK_UART2_MUX 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 87) #define SCLK_UART2 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 88) #define SCLK_UART3_DIV 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 89) #define SCLK_UART3_FRAC 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 90) #define SCLK_UART3_MUX 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 91) #define SCLK_UART3 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 92) #define SCLK_UART4_DIV 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 93) #define SCLK_UART4_FRAC 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 94) #define SCLK_UART4_MUX 27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 95) #define SCLK_UART4 28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 96) #define SCLK_UART5_DIV 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 97) #define SCLK_UART5_FRAC 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 98) #define SCLK_UART5_MUX 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 99) #define SCLK_UART5 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define CLK_I2C1 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define CLK_I2C3 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define CLK_I2C4 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define CLK_I2C5 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define CLK_SPI1 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) #define CLK_CAPTURE_PWM2 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) #define CLK_PWM2 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define DBCLK_GPIO1 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define DBCLK_GPIO2 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define DBCLK_GPIO3 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define DBCLK_GPIO4 43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define CLK_SARADC 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define CLK_TIMER0 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define CLK_TIMER1 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define CLK_TIMER2 47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define CLK_TIMER3 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define CLK_TIMER4 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define CLK_TIMER5 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define CLK_CAN 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define CLK_NPU_TSADC 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define CLK_NPU_TSADCPHY 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define CLK_CPU_TSADC 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define CLK_CPU_TSADCPHY 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define CLK_CRYPTO_CORE 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define CLK_CRYPTO_PKA 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define MCLK_I2S0_TX_DIV 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define MCLK_I2S0_TX_FRACDIV 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define MCLK_I2S0_TX_MUX 60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define MCLK_I2S0_TX 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define MCLK_I2S0_RX_DIV 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define MCLK_I2S0_RX_FRACDIV 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define MCLK_I2S0_RX_MUX 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define MCLK_I2S0_RX 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define MCLK_I2S0_TX_OUT2IO 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define MCLK_I2S0_RX_OUT2IO 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define MCLK_I2S1_DIV 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define MCLK_I2S1_FRACDIV 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) #define MCLK_I2S1_MUX 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) #define MCLK_I2S1 71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define MCLK_I2S1_OUT2IO 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define MCLK_I2S2_DIV 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define MCLK_I2S2_FRACDIV 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define MCLK_I2S2_MUX 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define MCLK_I2S2 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define MCLK_I2S2_OUT2IO 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define MCLK_PDM 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define SCLK_ADUPWM_DIV 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define SCLK_AUDPWM_FRACDIV 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define SCLK_AUDPWM_MUX 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define SCLK_AUDPWM 82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define CLK_ACDCDIG_ADC 83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define CLK_ACDCDIG_DAC 84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define CLK_ACDCDIG_I2C 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define CLK_VENC_CORE 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define CLK_VDEC_CORE 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define CLK_VDEC_CA 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define CLK_VDEC_HEVC_CA 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define CLK_RGA_CORE 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define CLK_IEP_CORE 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define CLK_ISP_DIV 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define CLK_ISP_NP5 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define CLK_ISP_NUX 94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define CLK_ISP 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define CLK_CIF_OUT_DIV 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define CLK_CIF_OUT_FRACDIV 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) #define CLK_CIF_OUT_MUX 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_CIF_OUT 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) #define CLK_MIPICSI_OUT_DIV 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) #define CLK_MIPICSI_OUT_FRACDIV 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define CLK_MIPICSI_OUT_MUX 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define CLK_MIPICSI_OUT 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define CLK_ISPP_DIV 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define CLK_ISPP_NP5 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define CLK_ISPP_NUX 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define CLK_ISPP 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define CLK_SDMMC 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SCLK_SDMMC_DRV 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define SCLK_SDMMC_SAMPLE 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define CLK_SDIO 111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define SCLK_SDIO_DRV 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define SCLK_SDIO_SAMPLE 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) #define CLK_EMMC 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SCLK_EMMC_DRV 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SCLK_EMMC_SAMPLE 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define CLK_NANDC 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define SCLK_SFC 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define CLK_USBHOST_UTMI_OHCI 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define CLK_USBOTG_REF 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define CLK_GMAC_DIV 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define CLK_GMAC_RGMII_M0 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define CLK_GMAC_SRC_M0 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define CLK_GMAC_RGMII_M1 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define CLK_GMAC_SRC_M1 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define CLK_GMAC_SRC 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define CLK_GMAC_REF 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define CLK_GMAC_TX_SRC 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define CLK_GMAC_TX_DIV5 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define CLK_GMAC_TX_DIV50 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) #define RGMII_MODE_CLK 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define CLK_GMAC_RX_SRC 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define CLK_GMAC_RX_DIV2 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define CLK_GMAC_RX_DIV20 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define RMII_MODE_CLK 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define CLK_GMAC_TX_RX 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define CLK_GMAC_PTPREF 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define CLK_GMAC_ETHERNET_OUT 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define CLK_DDRPHY 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define CLK_DDR_MON 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define TMCLK_DDR_MON 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define CLK_NPU_DIV 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define CLK_NPU_NP5 143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define CLK_CORE_NPU 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define CLK_CORE_NPUPVTM 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define CLK_NPUPVTM 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define SCLK_DDRCLK 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) #define CLK_OTP 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) /* dclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define DCLK_DECOM 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define DCLK_VOP_DIV 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define DCLK_VOP_FRACDIV 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define DCLK_VOP_MUX 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define DCLK_VOP 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define DCLK_CIF 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define DCLK_CIFLITE 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) /* aclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define ACLK_PDBUS 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define ACLK_DMAC 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define ACLK_DCF 162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) #define ACLK_SPINLOCK 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define ACLK_DECOM 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define ACLK_PDCRYPTO 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define ACLK_CRYPTO 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define ACLK_PDVEPU 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define ACLK_VENC 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define ACLK_PDVDEC 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define ACLK_PDJPEG 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define ACLK_VDEC 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define ACLK_JPEG 172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define ACLK_PDVO 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define ACLK_RGA 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define ACLK_VOP 175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define ACLK_IEP 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) #define ACLK_PDVI_DIV 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ACLK_PDVI_NP5 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define ACLK_PDVI 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define ACLK_ISP 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define ACLK_CIF 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define ACLK_CIFLITE 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define ACLK_PDISPP_DIV 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define ACLK_PDISPP_NP5 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define ACLK_PDISPP 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define ACLK_ISPP 186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define ACLK_PDPHP 187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define ACLK_PDUSB 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ACLK_USBOTG 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define ACLK_PDGMAC 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define ACLK_GMAC 191
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define ACLK_PDNPU_DIV 192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define ACLK_PDNPU_NP5 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) #define ACLK_PDNPU 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define ACLK_NPU 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) /* hclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define HCLK_PDCORE_NIU 200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define HCLK_PDUSB 201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define HCLK_PDCRYPTO 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define HCLK_CRYPTO 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) #define HCLK_PDAUDIO 204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define HCLK_I2S0 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define HCLK_I2S1 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define HCLK_I2S2 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define HCLK_PDM 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define HCLK_AUDPWM 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define HCLK_PDVEPU 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define HCLK_VENC 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define HCLK_PDVDEC 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define HCLK_PDJPEG 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define HCLK_VDEC 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define HCLK_JPEG 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define HCLK_PDVO 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define HCLK_RGA 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define HCLK_VOP 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define HCLK_IEP 219
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define HCLK_PDVI 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) #define HCLK_ISP 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define HCLK_CIF 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define HCLK_CIFLITE 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define HCLK_PDISPP 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define HCLK_ISPP 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define HCLK_PDPHP 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define HCLK_PDSDMMC 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define HCLK_SDMMC 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define HCLK_PDSDIO 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define HCLK_SDIO 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define HCLK_PDNVM 231
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define HCLK_EMMC 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define HCLK_NANDC 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define HCLK_SFC 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define HCLK_SFCXIP 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define HCLK_PDBUS 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define HCLK_USBHOST 237
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) #define HCLK_USBHOST_ARB 238
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define HCLK_PDNPU 239
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define HCLK_NPU 240
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) /* pclk */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define PCLK_CPUPVTM 245
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define PCLK_PDBUS 246
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define PCLK_DCF 247
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define PCLK_WDT 248
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define PCLK_MAILBOX 249
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define PCLK_UART0 250
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define PCLK_UART2 251
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define PCLK_UART3 252
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define PCLK_UART4 253
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define PCLK_UART5 254
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define PCLK_I2C1 255
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define PCLK_I2C3 256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define PCLK_I2C4 257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define PCLK_I2C5 258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define PCLK_SPI1 259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) #define PCLK_PWM2 261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define PCLK_GPIO1 262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define PCLK_GPIO2 263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define PCLK_GPIO3 264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define PCLK_GPIO4 265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define PCLK_SARADC 266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define PCLK_TIMER 267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define PCLK_DECOM 268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PCLK_CAN 269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PCLK_NPU_TSADC 270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PCLK_CPU_TSADC 271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PCLK_ACDCDIG 272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define PCLK_PDVO 273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define PCLK_DSIHOST 274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define PCLK_PDVI 275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define PCLK_CSIHOST 276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) #define PCLK_PDGMAC 277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define PCLK_GMAC 278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define PCLK_PDDDR 279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define PCLK_DDR_MON 280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define PCLK_PDNPU 281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define PCLK_NPUPVTM 282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PCLK_PDTOP 283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define PCLK_TOPCRU 284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PCLK_TOPGRF 285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define PCLK_CPUEMADET 286
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define PCLK_DDRPHY 287
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define PCLK_DSIPHY 289
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define PCLK_CSIPHY0 290
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) #define PCLK_CSIPHY1 291
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #define PCLK_USBPHY_HOST 292
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 354) #define PCLK_USBPHY_OTG 293
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 355) #define PCLK_OTP 294
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 356)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 357) #define CLK_NR_CLKS (PCLK_OTP + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 358)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 359) /* pmu soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 360)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 361) /* pmu_cru_softrst_con0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 362) #define SRST_PDPMU_NIU_P 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 363) #define SRST_PMU_SGRF_P 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 364) #define SRST_PMU_SGRF_REMAP_P 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 365) #define SRST_I2C0_P 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 366) #define SRST_I2C0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 367) #define SRST_I2C2_P 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 368) #define SRST_I2C2 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 369) #define SRST_UART1_P 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 370) #define SRST_UART1 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 371) #define SRST_PWM0_P 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 372) #define SRST_PWM0 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 373) #define SRST_PWM1_P 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 374) #define SRST_PWM1 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 375) #define SRST_DDR_FAIL_SAFE 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 376)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 377) /* pmu_cru_softrst_con1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 378) #define SRST_GPIO0_P 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 379) #define SRST_GPIO0_DB 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 380) #define SRST_SPI0_P 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 381) #define SRST_SPI0 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 382) #define SRST_PMUGRF_P 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 383) #define SRST_CHIPVEROTP_P 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 384) #define SRST_PMUPVTM 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 385) #define SRST_PMUPVTM_P 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 386) #define SRST_PMUCRU_P 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 387)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 388) /* soft-reset indices */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 389)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 390) /* cru_softrst_con0 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 391) #define SRST_CORE0_PO 0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 392) #define SRST_CORE1_PO 1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 393) #define SRST_CORE2_PO 2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 394) #define SRST_CORE3_PO 3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 395) #define SRST_CORE0 4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 396) #define SRST_CORE1 5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 397) #define SRST_CORE2 6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 398) #define SRST_CORE3 7
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 399) #define SRST_CORE0_DBG 8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 400) #define SRST_CORE1_DBG 9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 401) #define SRST_CORE2_DBG 10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 402) #define SRST_CORE3_DBG 11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 403) #define SRST_NL2 12
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 404) #define SRST_CORE_NIU_A 13
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 405) #define SRST_DBG_DAPLITE_P 14
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 406) #define SRST_DAPLITE_P 15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 407)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 408) /* cru_softrst_con1 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 409) #define SRST_PDBUS_NIU1_A 16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 410) #define SRST_PDBUS_NIU1_H 17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 411) #define SRST_PDBUS_NIU1_P 18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 412) #define SRST_PDBUS_NIU2_A 19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 413) #define SRST_PDBUS_NIU2_H 20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 414) #define SRST_PDBUS_NIU3_A 21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 415) #define SRST_PDBUS_NIU3_H 22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 416) #define SRST_PDBUS_HOLD_NIU1_A 23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 417) #define SRST_DBG_NIU_P 24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 418) #define SRST_PDCORE_NIIU_H 25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 419) #define SRST_MUC_NIU 26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 420) #define SRST_DCF_A 29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 421) #define SRST_DCF_P 30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 422) #define SRST_SYSTEM_SRAM_A 31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 423)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 424) /* cru_softrst_con2 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 425) #define SRST_I2C1_P 32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 426) #define SRST_I2C1 33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 427) #define SRST_I2C3_P 34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 428) #define SRST_I2C3 35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 429) #define SRST_I2C4_P 36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 430) #define SRST_I2C4 37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 431) #define SRST_I2C5_P 38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 432) #define SRST_I2C5 39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 433) #define SRST_SPI1_P 40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 434) #define SRST_SPI1 41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 435) #define SRST_MCU_CORE 42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 436) #define SRST_PWM2_P 44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 437) #define SRST_PWM2 45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 438) #define SRST_SPINLOCK_A 46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 439)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 440) /* cru_softrst_con3 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 441) #define SRST_UART0_P 48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 442) #define SRST_UART0 49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 443) #define SRST_UART2_P 50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 444) #define SRST_UART2 51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 445) #define SRST_UART3_P 52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 446) #define SRST_UART3 53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 447) #define SRST_UART4_P 54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 448) #define SRST_UART4 55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 449) #define SRST_UART5_P 56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 450) #define SRST_UART5 57
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 451) #define SRST_WDT_P 58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 452) #define SRST_SARADC_P 59
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 453) #define SRST_GRF_P 61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 454) #define SRST_TIMER_P 62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 455) #define SRST_MAILBOX_P 63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 456)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 457) /* cru_softrst_con4 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 458) #define SRST_TIMER0 64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 459) #define SRST_TIMER1 65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 460) #define SRST_TIMER2 66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 461) #define SRST_TIMER3 67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 462) #define SRST_TIMER4 68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 463) #define SRST_TIMER5 69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 464) #define SRST_INTMUX_P 70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 465) #define SRST_GPIO1_P 72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 466) #define SRST_GPIO1_DB 73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 467) #define SRST_GPIO2_P 74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 468) #define SRST_GPIO2_DB 75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 469) #define SRST_GPIO3_P 76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 470) #define SRST_GPIO3_DB 77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 471) #define SRST_GPIO4_P 78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 472) #define SRST_GPIO4_DB 79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 473)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 474) /* cru_softrst_con5 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 475) #define SRST_CAN_P 80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 476) #define SRST_CAN 81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 477) #define SRST_DECOM_A 85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 478) #define SRST_DECOM_P 86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 479) #define SRST_DECOM_D 87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 480) #define SRST_PDCRYPTO_NIU_A 88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 481) #define SRST_PDCRYPTO_NIU_H 89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 482) #define SRST_CRYPTO_A 90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 483) #define SRST_CRYPTO_H 91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 484) #define SRST_CRYPTO_CORE 92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 485) #define SRST_CRYPTO_PKA 93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 486) #define SRST_SGRF_P 95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 487)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 488) /* cru_softrst_con6 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 489) #define SRST_PDAUDIO_NIU_H 96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 490) #define SRST_PDAUDIO_NIU_P 97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 491) #define SRST_I2S0_H 98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 492) #define SRST_I2S0_TX_M 99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 493) #define SRST_I2S0_RX_M 100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 494) #define SRST_I2S1_H 101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 495) #define SRST_I2S1_M 102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 496) #define SRST_I2S2_H 103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 497) #define SRST_I2S2_M 104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 498) #define SRST_PDM_H 105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 499) #define SRST_PDM_M 106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 500) #define SRST_AUDPWM_H 107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 501) #define SRST_AUDPWM 108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 502) #define SRST_ACDCDIG_P 109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 503) #define SRST_ACDCDIG 110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 504)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 505) /* cru_softrst_con7 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 506) #define SRST_PDVEPU_NIU_A 112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 507) #define SRST_PDVEPU_NIU_H 113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 508) #define SRST_VENC_A 114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 509) #define SRST_VENC_H 115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 510) #define SRST_VENC_CORE 116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 511) #define SRST_PDVDEC_NIU_A 117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 512) #define SRST_PDVDEC_NIU_H 118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 513) #define SRST_VDEC_A 119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 514) #define SRST_VDEC_H 120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 515) #define SRST_VDEC_CORE 121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 516) #define SRST_VDEC_CA 122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 517) #define SRST_VDEC_HEVC_CA 123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 518) #define SRST_PDJPEG_NIU_A 124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 519) #define SRST_PDJPEG_NIU_H 125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 520) #define SRST_JPEG_A 126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 521) #define SRST_JPEG_H 127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 522)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 523) /* cru_softrst_con8 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 524) #define SRST_PDVO_NIU_A 128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 525) #define SRST_PDVO_NIU_H 129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 526) #define SRST_PDVO_NIU_P 130
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 527) #define SRST_RGA_A 131
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 528) #define SRST_RGA_H 132
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 529) #define SRST_RGA_CORE 133
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 530) #define SRST_VOP_A 134
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 531) #define SRST_VOP_H 135
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 532) #define SRST_VOP_D 136
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 533) #define SRST_TXBYTEHS_DSIHOST 137
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 534) #define SRST_DSIHOST_P 138
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 535) #define SRST_IEP_A 139
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 536) #define SRST_IEP_H 140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 537) #define SRST_IEP_CORE 141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 538) #define SRST_ISP_RX_P 142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 539)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 540) /* cru_softrst_con9 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 541) #define SRST_PDVI_NIU_A 144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 542) #define SRST_PDVI_NIU_H 145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 543) #define SRST_PDVI_NIU_P 146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 544) #define SRST_ISP 147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 545) #define SRST_CIF_A 148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 546) #define SRST_CIF_H 149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 547) #define SRST_CIF_D 150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 548) #define SRST_CIF_P 151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 549) #define SRST_CIF_I 152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 550) #define SRST_CIF_RX_P 153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 551) #define SRST_PDISPP_NIU_A 154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 552) #define SRST_PDISPP_NIU_H 155
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 553) #define SRST_ISPP_A 156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 554) #define SRST_ISPP_H 157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 555) #define SRST_ISPP 158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 556) #define SRST_CSIHOST_P 159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 557)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 558) /* cru_softrst_con10 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 559) #define SRST_PDPHPMID_NIU_A 160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 560) #define SRST_PDPHPMID_NIU_H 161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 561) #define SRST_PDNVM_NIU_H 163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 562) #define SRST_SDMMC_H 164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 563) #define SRST_SDIO_H 165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 564) #define SRST_EMMC_H 166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 565) #define SRST_SFC_H 167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 566) #define SRST_SFCXIP_H 168
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 567) #define SRST_SFC 169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 568) #define SRST_NANDC_H 170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 569) #define SRST_NANDC 171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 570) #define SRST_PDSDMMC_H 173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 571) #define SRST_PDSDIO_H 174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 572)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 573) /* cru_softrst_con11 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 574) #define SRST_PDUSB_NIU_A 176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 575) #define SRST_PDUSB_NIU_H 177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 576) #define SRST_USBHOST_H 178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 577) #define SRST_USBHOST_ARB_H 179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 578) #define SRST_USBHOST_UTMI 180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 579) #define SRST_USBOTG_A 181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 580) #define SRST_USBPHY_OTG_P 182
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 581) #define SRST_USBPHY_HOST_P 183
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 582) #define SRST_USBPHYPOR_OTG 184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 583) #define SRST_USBPHYPOR_HOST 185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 584) #define SRST_PDGMAC_NIU_A 188
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 585) #define SRST_PDGMAC_NIU_P 189
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 586) #define SRST_GMAC_A 190
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 587)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 588) /* cru_softrst_con12 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 589) #define SRST_DDR_DFICTL_P 193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 590) #define SRST_DDR_MON_P 194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 591) #define SRST_DDR_STANDBY_P 195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 592) #define SRST_DDR_GRF_P 196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 593) #define SRST_DDR_MSCH_P 197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 594) #define SRST_DDR_SPLIT_A 198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 595) #define SRST_DDR_MSCH 199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 596) #define SRST_DDR_DFICTL 202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 597) #define SRST_DDR_STANDBY 203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 598) #define SRST_NPUMCU_NIU 205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 599) #define SRST_DDRPHY_P 206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 600) #define SRST_DDRPHY 207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 601)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 602) /* cru_softrst_con13 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 603) #define SRST_PDNPU_NIU_A 208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 604) #define SRST_PDNPU_NIU_H 209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 605) #define SRST_PDNPU_NIU_P 210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 606) #define SRST_NPU_A 211
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 607) #define SRST_NPU_H 212
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 608) #define SRST_NPU 213
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 609) #define SRST_NPUPVTM_P 214
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 610) #define SRST_NPUPVTM 215
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 611) #define SRST_NPU_TSADC_P 216
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 612) #define SRST_NPU_TSADC 217
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 613) #define SRST_NPU_TSADCPHY 218
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 614) #define SRST_CIFLITE_A 220
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 615) #define SRST_CIFLITE_H 221
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 616) #define SRST_CIFLITE_D 222
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 617) #define SRST_CIFLITE_RX_P 223
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 618)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 619) /* cru_softrst_con14 */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 620) #define SRST_TOPNIU_P 224
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 621) #define SRST_TOPCRU_P 225
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 622) #define SRST_TOPGRF_P 226
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 623) #define SRST_CPUEMADET_P 227
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 624) #define SRST_CSIPHY0_P 228
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 625) #define SRST_CSIPHY1_P 229
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 626) #define SRST_DSIPHY_P 230
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 627) #define SRST_CPU_TSADC_P 232
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 628) #define SRST_CPU_TSADC 233
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 629) #define SRST_CPU_TSADCPHY 234
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 630) #define SRST_CPUPVTM_P 235
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 631) #define SRST_CPUPVTM 236
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 632)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 633) #endif
Orange Pi5 kernel
Deprecated Linux kernel 5.10.110 for OrangePi 5/5B/5+ boards
3 Commits
0 Branches
0 Tags