Orange Pi5 kernel

^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   1) /* SPDX-License-Identifier: (GPL-2.0+ OR MIT) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   2) /*
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   3)  * Copyright (c) 2016 Rockchip Electronics Co. Ltd.
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   4)  * Author: Shawn Lin <shawn.lin@rock-chips.com>
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   5)  */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   6) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   7) #ifndef _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   8) #define _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300   9) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  10) /* pll id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  11) #define PLL_APLL			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  12) #define PLL_DPLL			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  13) #define PLL_GPLL			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  14) #define ARMCLK				3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  15) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  16) /* sclk gates (special clocks) */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  17) #define SCLK_SPI0			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  18) #define SCLK_NANDC			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  19) #define SCLK_SDMMC			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  20) #define SCLK_SDIO			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  21) #define SCLK_EMMC			71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  22) #define SCLK_UART0			72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  23) #define SCLK_UART1			73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  24) #define SCLK_UART2			74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  25) #define SCLK_I2S0			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  26) #define SCLK_I2S1			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  27) #define SCLK_I2S2			77
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  28) #define SCLK_TIMER0			78
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  29) #define SCLK_TIMER1			79
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  30) #define SCLK_SFC			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  31) #define SCLK_SDMMC_DRV			81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  32) #define SCLK_SDIO_DRV			82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  33) #define SCLK_EMMC_DRV			83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  34) #define SCLK_SDMMC_SAMPLE		84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  35) #define SCLK_SDIO_SAMPLE		85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  36) #define SCLK_EMMC_SAMPLE		86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  37) #define SCLK_VENC_CORE			87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  38) #define SCLK_HEVC_CORE			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  39) #define SCLK_HEVC_CABAC			89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  40) #define SCLK_PWM0_PMU			90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  41) #define SCLK_I2C0_PMU			91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  42) #define SCLK_WIFI			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  43) #define SCLK_CIFOUT			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  44) #define SCLK_MIPI_CSI_OUT		94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  45) #define SCLK_CIF0			95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  46) #define SCLK_CIF1			96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  47) #define SCLK_CIF2			97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  48) #define SCLK_CIF3			98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  49) #define SCLK_DSP			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  50) #define SCLK_DSP_IOP			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  51) #define SCLK_DSP_EPP			101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  52) #define SCLK_DSP_EDP			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  53) #define SCLK_DSP_EDAP			103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  54) #define SCLK_CVBS_HOST			104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  55) #define SCLK_HDMI_SFR			105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  56) #define SCLK_HDMI_CEC			106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  57) #define SCLK_CRYPTO			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  58) #define SCLK_SPI			108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  59) #define SCLK_SARADC			109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  60) #define SCLK_TSADC			110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  61) #define SCLK_MAC_PRE			111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  62) #define SCLK_MAC			112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  63) #define SCLK_MAC_RX			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  64) #define SCLK_MAC_REF			114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  65) #define SCLK_MAC_REFOUT			115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  66) #define SCLK_DSP_PFM			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  67) #define SCLK_RGA			117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  68) #define SCLK_I2C1			118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  69) #define SCLK_I2C2			119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  70) #define SCLK_I2C3			120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  71) #define SCLK_PWM			121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  72) #define SCLK_ISP			122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  73) #define SCLK_USBPHY			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  74) #define SCLK_I2S0_SRC			124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  75) #define SCLK_I2S1_SRC			125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  76) #define SCLK_I2S2_SRC			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  77) #define SCLK_UART0_SRC			127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  78) #define SCLK_UART1_SRC			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  79) #define SCLK_UART2_SRC			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  80) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  81) #define DCLK_VOP_SRC			185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  82) #define DCLK_HDMIPHY			186
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  83) #define DCLK_VOP			187
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  84) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  85) /* aclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  86) #define ACLK_DMAC			192
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  87) #define ACLK_PRE			193
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  88) #define ACLK_CORE			194
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  89) #define ACLK_ENMCORE			195
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  90) #define ACLK_RKVENC			196
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  91) #define ACLK_RKVDEC			197
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  92) #define ACLK_VPU			198
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  93) #define ACLK_CIF0			199
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  94) #define ACLK_VIO0			200
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  95) #define ACLK_VIO1			201
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  96) #define ACLK_VOP			202
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  97) #define ACLK_IEP			203
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  98) #define ACLK_RGA			204
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300  99) #define ACLK_ISP			205
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 100) #define ACLK_CIF1			206
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 101) #define ACLK_CIF2			207
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 102) #define ACLK_CIF3			208
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 103) #define ACLK_PERI			209
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 104) #define ACLK_GMAC			210
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 105) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 106) /* pclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 107) #define PCLK_GPIO1			256
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 108) #define PCLK_GPIO2			257
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 109) #define PCLK_GPIO3			258
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 110) #define PCLK_GRF			259
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 111) #define PCLK_I2C1			260
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 112) #define PCLK_I2C2			261
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 113) #define PCLK_I2C3			262
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 114) #define PCLK_SPI			263
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 115) #define PCLK_SFC			264
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 116) #define PCLK_UART0			265
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 117) #define PCLK_UART1			266
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 118) #define PCLK_UART2			267
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 119) #define PCLK_TSADC			268
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 120) #define PCLK_PWM			269
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 121) #define PCLK_TIMER			270
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 122) #define PCLK_PERI			271
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 123) #define PCLK_GPIO0_PMU			272
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 124) #define PCLK_I2C0_PMU			273
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 125) #define PCLK_PWM0_PMU			274
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 126) #define PCLK_ISP			275
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 127) #define PCLK_VIO			276
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 128) #define PCLK_MIPI_DSI			277
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 129) #define PCLK_HDMI_CTRL			278
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 130) #define PCLK_SARADC			279
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 131) #define PCLK_DSP_CFG			280
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 132) #define PCLK_BUS			281
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 133) #define PCLK_EFUSE0			282
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 134) #define PCLK_EFUSE1			283
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 135) #define PCLK_WDT			284
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 136) #define PCLK_GMAC			285
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 137) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 138) /* hclk gates */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 139) #define HCLK_I2S0_8CH			320
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 140) #define HCLK_I2S1_2CH			321
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 141) #define HCLK_I2S2_2CH			322
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 142) #define HCLK_NANDC			323
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 143) #define HCLK_SDMMC			324
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 144) #define HCLK_SDIO			325
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 145) #define HCLK_EMMC			326
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 146) #define HCLK_PERI			327
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 147) #define HCLK_SFC			328
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 148) #define HCLK_RKVENC			329
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 149) #define HCLK_RKVDEC			330
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 150) #define HCLK_CIF0			331
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 151) #define HCLK_VIO			332
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 152) #define HCLK_VOP			333
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 153) #define HCLK_IEP			334
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 154) #define HCLK_RGA			335
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 155) #define HCLK_ISP			336
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 156) #define HCLK_CRYPTO_MST			337
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 157) #define HCLK_CRYPTO_SLV			338
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 158) #define HCLK_HOST0			339
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 159) #define HCLK_OTG			340
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 160) #define HCLK_CIF1			341
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 161) #define HCLK_CIF2			342
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 162) #define HCLK_CIF3			343
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 163) #define HCLK_BUS			344
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 164) #define HCLK_VPU			345
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 165) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 166) #define CLK_NR_CLKS			(HCLK_VPU + 1)
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 167) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 168) /* reset id */
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 169) #define SRST_CORE_PO_AD			0
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 170) #define SRST_CORE_AD			1
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 171) #define SRST_L2_AD			2
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 172) #define SRST_CPU_NIU_AD			3
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 173) #define SRST_CORE_PO			4
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 174) #define SRST_CORE			5
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 175) #define SRST_L2				6
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 176) #define SRST_CORE_DBG			8
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 177) #define PRST_DBG			9
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 178) #define RST_DAP				10
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 179) #define PRST_DBG_NIU			11
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 180) #define ARST_STRC_SYS_AD		15
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 181) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 182) #define SRST_DDRPHY_CLKDIV		16
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 183) #define SRST_DDRPHY			17
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 184) #define PRST_DDRPHY			18
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 185) #define PRST_HDMIPHY			19
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 186) #define PRST_VDACPHY			20
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 187) #define PRST_VADCPHY			21
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 188) #define PRST_MIPI_CSI_PHY		22
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 189) #define PRST_MIPI_DSI_PHY		23
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 190) #define PRST_ACODEC			24
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 191) #define ARST_BUS_NIU			25
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 192) #define PRST_TOP_NIU			26
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 193) #define ARST_INTMEM			27
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 194) #define HRST_ROM			28
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 195) #define ARST_DMAC			29
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 196) #define SRST_MSCH_NIU			30
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 197) #define PRST_MSCH_NIU			31
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 198) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 199) #define PRST_DDRUPCTL			32
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 200) #define NRST_DDRUPCTL			33
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 201) #define PRST_DDRMON			34
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 202) #define HRST_I2S0_8CH			35
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 203) #define MRST_I2S0_8CH			36
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 204) #define HRST_I2S1_2CH			37
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 205) #define MRST_IS21_2CH			38
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 206) #define HRST_I2S2_2CH			39
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 207) #define MRST_I2S2_2CH			40
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 208) #define HRST_CRYPTO			41
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 209) #define SRST_CRYPTO			42
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 210) #define PRST_SPI			43
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 211) #define SRST_SPI			44
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 212) #define PRST_UART0			45
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 213) #define PRST_UART1			46
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 214) #define PRST_UART2			47
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 215) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 216) #define SRST_UART0			48
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 217) #define SRST_UART1			49
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 218) #define SRST_UART2			50
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 219) #define PRST_I2C1			51
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 220) #define PRST_I2C2			52
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 221) #define PRST_I2C3			53
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 222) #define SRST_I2C1			54
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 223) #define SRST_I2C2			55
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 224) #define SRST_I2C3			56
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 225) #define PRST_PWM1			58
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 226) #define SRST_PWM1			60
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 227) #define PRST_WDT			61
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 228) #define PRST_GPIO1			62
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 229) #define PRST_GPIO2			63
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 230) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 231) #define PRST_GPIO3			64
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 232) #define PRST_GRF			65
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 233) #define PRST_EFUSE			66
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 234) #define PRST_EFUSE512			67
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 235) #define PRST_TIMER0			68
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 236) #define SRST_TIMER0			69
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 237) #define SRST_TIMER1			70
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 238) #define PRST_TSADC			71
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 239) #define SRST_TSADC			72
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 240) #define PRST_SARADC			73
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 241) #define SRST_SARADC			74
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 242) #define HRST_SYSBUS			75
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 243) #define PRST_USBGRF			76
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 244) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 245) #define ARST_PERIPH_NIU			80
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 246) #define HRST_PERIPH_NIU			81
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 247) #define PRST_PERIPH_NIU			82
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 248) #define HRST_PERIPH			83
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 249) #define HRST_SDMMC			84
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 250) #define HRST_SDIO			85
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 251) #define HRST_EMMC			86
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 252) #define HRST_NANDC			87
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 253) #define NRST_NANDC			88
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 254) #define HRST_SFC			89
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 255) #define SRST_SFC			90
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 256) #define ARST_GMAC			91
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 257) #define HRST_OTG			92
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 258) #define SRST_OTG			93
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 259) #define SRST_OTG_ADP			94
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 260) #define HRST_HOST0			95
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 261) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 262) #define HRST_HOST0_AUX			96
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 263) #define HRST_HOST0_ARB			97
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 264) #define SRST_HOST0_EHCIPHY		98
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 265) #define SRST_HOST0_UTMI			99
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 266) #define SRST_USBPOR			100
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 267) #define SRST_UTMI0			101
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 268) #define SRST_UTMI1			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 269) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 270) #define ARST_VIO0_NIU			102
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 271) #define ARST_VIO1_NIU			103
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 272) #define HRST_VIO_NIU			104
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 273) #define PRST_VIO_NIU			105
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 274) #define ARST_VOP			106
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 275) #define HRST_VOP			107
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 276) #define DRST_VOP			108
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 277) #define ARST_IEP			109
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 278) #define HRST_IEP			110
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 279) #define ARST_RGA			111
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 280) #define HRST_RGA			112
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 281) #define SRST_RGA			113
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 282) #define PRST_CVBS			114
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 283) #define PRST_HDMI			115
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 284) #define SRST_HDMI			116
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 285) #define PRST_MIPI_DSI			117
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 286) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 287) #define ARST_ISP_NIU			118
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 288) #define HRST_ISP_NIU			119
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 289) #define HRST_ISP			120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 290) #define SRST_ISP			121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 291) #define ARST_VIP0			122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 292) #define HRST_VIP0			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 293) #define PRST_VIP0			124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 294) #define ARST_VIP1			125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 295) #define HRST_VIP1			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 296) #define PRST_VIP1			127
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 297) #define ARST_VIP2			128
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 298) #define HRST_VIP2			129
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 299) #define PRST_VIP2			120
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 300) #define ARST_VIP3			121
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 301) #define HRST_VIP3			122
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 302) #define PRST_VIP4			123
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 303) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 304) #define PRST_CIF1TO4			124
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 305) #define SRST_CVBS_CLK			125
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 306) #define HRST_CVBS			126
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 307) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 308) #define ARST_VPU_NIU			140
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 309) #define HRST_VPU_NIU			141
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 310) #define ARST_VPU			142
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 311) #define HRST_VPU			143
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 312) #define ARST_RKVDEC_NIU			144
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 313) #define HRST_RKVDEC_NIU			145
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 314) #define ARST_RKVDEC			146
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 315) #define HRST_RKVDEC			147
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 316) #define SRST_RKVDEC_CABAC		148
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 317) #define SRST_RKVDEC_CORE		149
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 318) #define ARST_RKVENC_NIU			150
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 319) #define HRST_RKVENC_NIU			151
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 320) #define ARST_RKVENC			152
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 321) #define HRST_RKVENC			153
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 322) #define SRST_RKVENC_CORE		154
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 323) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 324) #define SRST_DSP_CORE			156
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 325) #define SRST_DSP_SYS			157
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 326) #define SRST_DSP_GLOBAL			158
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 327) #define SRST_DSP_OECM			159
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 328) #define PRST_DSP_IOP_NIU		160
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 329) #define ARST_DSP_EPP_NIU		161
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 330) #define ARST_DSP_EDP_NIU		162
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 331) #define PRST_DSP_DBG_NIU		163
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 332) #define PRST_DSP_CFG_NIU		164
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 333) #define PRST_DSP_GRF			165
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 334) #define PRST_DSP_MAILBOX		166
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 335) #define PRST_DSP_INTC			167
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 336) #define PRST_DSP_PFM_MON		169
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 337) #define SRST_DSP_PFM_MON		170
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 338) #define ARST_DSP_EDAP_NIU		171
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 339) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 340) #define SRST_PMU			172
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 341) #define SRST_PMU_I2C0			173
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 342) #define PRST_PMU_I2C0			174
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 343) #define PRST_PMU_GPIO0			175
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 344) #define PRST_PMU_INTMEM			176
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 345) #define PRST_PMU_PWM0			177
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 346) #define SRST_PMU_PWM0			178
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 347) #define PRST_PMU_GRF			179
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 348) #define SRST_PMU_NIU			180
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 349) #define SRST_PMU_PVTM			181
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 350) #define ARST_DSP_EDP_PERF		184
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 351) #define ARST_DSP_EPP_PERF		185
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 352) 
^8f3ce5b39 (kx 2023-10-28 12:00:06 +0300 353) #endif /* _DT_BINDINGS_CLK_ROCKCHIP_RV1108_H */